AXI4_LiteMM/sources_1/imports/AXI4_liteMM/Enable_gen.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: Enable_gen
// Description: 
// The Module generates the enable signal for
// 
//////////////////////////////////////////////////////////////////////////////////


module Enable_gen(clk,stop,sys_rst_n,en_in,en_out);
input clk,stop,sys_rst_n,en_in;
output reg en_out;

reg tmp_out;

assign en_out1 = tmp_out | en_in;         // OR gate.
always@(posedge clk or posedge stop)   // FF with asyn rst_n.
begin
    if (stop)
        begin
         tmp_out <= 1'b0;
        end     
     else
        begin
          tmp_out <= en_out1;
        end
end

always@(posedge clk)
  begin
    if(!sys_rst_n)
       begin
            en_out <= 1'b0;
           end     
        else
           begin
             en_out <= en_out1;
           end
  end
endmodule