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Enable_gen.v 867 B

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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Module Name: Enable_gen
  4. // Description:
  5. // The Module generates the enable signal for
  6. //
  7. //////////////////////////////////////////////////////////////////////////////////
  8. module Enable_gen(clk,stop,sys_rst_n,en_in,en_out);
  9. input clk,stop,sys_rst_n,en_in;
  10. output reg en_out;
  11. reg tmp_out;
  12. assign en_out1 = tmp_out | en_in; // OR gate.
  13. always@(posedge clk or posedge stop) // FF with asyn rst_n.
  14. begin
  15. if (stop)
  16. begin
  17. tmp_out <= 1'b0;
  18. end
  19. else
  20. begin
  21. tmp_out <= en_out1;
  22. end
  23. end
  24. always@(posedge clk)
  25. begin
  26. if(!sys_rst_n)
  27. begin
  28. en_out <= 1'b0;
  29. end
  30. else
  31. begin
  32. en_out <= en_out1;
  33. end
  34. end
  35. endmodule