2 Commits

Author SHA1 Message Date
  vikram b30ddca5ea Controlled AWREADY v3 3 years ago
  abhigna 5988bcaff5 AWREADY_AWVALID v2 3 years ago
2 changed files with 62 additions and 36 deletions
Split View
  1. +42
    -24
      sim_1/imports/sim_1/tb_axi4_Lite_MM.v
  2. +20
    -12
      sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv

+ 42
- 24
sim_1/imports/sim_1/tb_axi4_Lite_MM.v View File

@@ -96,51 +96,64 @@ module tb_axi4_Lite_MM;
s_axi_wdata = 32'h11_44_33_22;
s_axi_wvalid = 1;
s_axi_bready = 1;
#8
s_axi_awvalid = 0; // added on 23022021.
s_axi_wvalid = 0;
#8;
//s_axi_awaddr = 18'h04;
//s_axi_wdata = 32'haa_bb_cc_ff;
#8;
s_axi_araddr = 18'h0C; // read
s_axi_arvalid = 1;
s_axi_rready = 1;
// #8
// s_axi_awvalid = 0; // added on 23022021.
// s_axi_wvalid = 0;
// #8;
// //s_axi_awaddr = 18'h04;
// //s_axi_wdata = 32'haa_bb_cc_ff;
// #8;
// s_axi_araddr = 18'h0C; // read
// s_axi_arvalid = 1;
// s_axi_rready = 1;
#8;
// #4;
#24;
s_axi_arvalid = 0;
// s_axi_araddr = 18'h04;
// s_axi_arvalid = 0;
s_axi_aresetn = 1; // write
s_axi_awvalid = 1;
s_axi_wvalid = 1;
s_axi_awaddr = 18'h10;
s_axi_wdata = 32'h88_77_66_55; //66_55_77_88;
s_axi_wvalid = 1;
//s_axi_bready = 1;
#12
s_axi_awvalid = 0; // added on 23022021.
s_axi_wvalid = 0;
// #12
// s_axi_awvalid = 0; // added on 23022021.
// s_axi_wvalid = 0;
#12
s_axi_araddr = 18'h10;
#4 s_axi_arvalid = 1;
s_axi_rready = 1;
// #12
// s_axi_araddr = 18'h10;
// #4 s_axi_arvalid = 1;
// s_axi_rready = 1;
#8;
#28;
s_axi_arvalid = 0; // write
s_axi_awvalid = 1;
s_axi_awaddr = 18'h1C;
s_axi_wdata = 32'h22_44_88_aa; //66_55_77_88;
s_axi_wvalid = 1;
//s_axi_bready = 1;
#28;
s_axi_araddr = 18'h0C; // read
s_axi_arvalid = 1;
s_axi_rready = 1;
#24;
s_axi_araddr = 18'h10;
s_axi_arvalid = 1;
s_axi_rready = 1;
#12;
// #12;
#24;
s_axi_araddr = 18'h1C; // read
#4 s_axi_arvalid = 1;
s_axi_arvalid = 1;
s_axi_rready = 1;
#8;
s_axi_arvalid = 0;
//#8;
// s_axi_arvalid = 0;
/* repeat(8)
begin
@@ -155,4 +168,9 @@ module tb_axi4_Lite_MM;
end

always #2 s_axi_aclk = ~s_axi_aclk;
always @(posedge s_axi_wready or posedge s_axi_awready)
begin
#8 s_axi_awvalid = 1'b0;
s_axi_wvalid = 1'b0;
end
endmodule

+ 20
- 12
sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv View File

@@ -119,6 +119,8 @@
//wire we;
//wire en;
//wire [1:0]select;
reg axi_awready1; // added for aw_w_ready control signals.
reg axi_wready1; // added for aw_w_ready control signals.
reg [(C_S_AXI_DATA_WIDTH/4)-1:0] temp_slv_reg;
reg s_data_done,s_data_done_1; // Enable when all the data written in slv_reg0
wire read_en; // Enable when address is valid
@@ -159,20 +161,26 @@
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
if (!wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b0;
else
axi_awready <= 1'b1;
$display($time,"\t axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
if (!wadr_dne) // adde for control of AWready.232022021.
begin
axi_awready <= 1'b0;
$display($time,"\tIF Passed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
end
else
begin
axi_awready <= 1'b1;
$display($time,"\tIF Failed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
end
end
else
begin
/* if (!wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b0;
if (wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b1;
else
axi_awready <= 1'b1;*/
axi_awready <= 1'b0;
axi_awready <= 1'b0;
// axi_awready <= 1'b0;
$display($time,"\tELSE axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
end
end
end
@@ -224,7 +232,7 @@
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_AWVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
@@ -441,7 +449,7 @@
//Enable_gen READ_ADDR_EN(.clk(S_AXI_ACLK),.rst(radr_dne),.en_in(slv_reg_rden),.en_out(read_en));
Enable_gen READ_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(radr_dne),.en_in(slv_reg_rden),.en_out(read_en));
Enable_gen WRITE_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(wadr_dne),.en_in(s_data_done),.en_out(write_en)); //.en_in(slv_reg_wren),.en_out(write_en));
Enable_gen WRITE_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(wadr_dne),.en_in(slv_reg_wren),.en_out(write_en)); //.en_in(s_data_done),.en_out(write_en));
always_comb


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