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AW_ready_valid_handshake

master
abhigna 3 years ago
parent
commit
7189c0e931
3 changed files with 28 additions and 12 deletions
  1. +6
    -0
      sim_1/imports/sim_1/tb_axi4_Lite_MM.v
  2. +6
    -6
      sources_1/imports/AXI4_liteMM/adderss_gen1.v
  3. +16
    -6
      sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv

+ 6
- 0
sim_1/imports/sim_1/tb_axi4_Lite_MM.v View File

@@ -96,6 +96,9 @@ module tb_axi4_Lite_MM;
s_axi_wdata = 32'h11_44_33_22;
s_axi_wvalid = 1;
s_axi_bready = 1;
#8
s_axi_awvalid = 0; // added on 23022021.
s_axi_wvalid = 0;
#8;
//s_axi_awaddr = 18'h04;
//s_axi_wdata = 32'haa_bb_cc_ff;
@@ -114,6 +117,9 @@ module tb_axi4_Lite_MM;
s_axi_wdata = 32'h88_77_66_55; //66_55_77_88;
s_axi_wvalid = 1;
//s_axi_bready = 1;
#12
s_axi_awvalid = 0; // added on 23022021.
s_axi_wvalid = 0;
#12
s_axi_araddr = 18'h10;


+ 6
- 6
sources_1/imports/AXI4_liteMM/adderss_gen1.v View File

@@ -38,19 +38,19 @@ wire [17:0] addr_out;

always @ (posedge core_clk)
begin
if (!rst_n)
if (!(rst_n && en_cnt)) // addded on 23022021.
cnt <= 2'b00;
else if (en_cnt)
begin
cnt <= cnt + 1'b1;
end
else
begin
if (cnt != 2'b00) // addded on 22022021.
cnt <= 2'b00; // addded on 22022021.
else // addded on 22022021.
// begin
// if (cnt != 2'b00) // addded on 22022021.
// cnt <= 2'b00; // addded on 22022021.
// else // addded on 22022021.
cnt <= cnt;
end
//end
end


+ 16
- 6
sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv View File

@@ -152,16 +152,26 @@
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID) //&&(~wadr_dne))
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
// expects no outstanding transactions.
axi_awready <= 1'b1;
if (!wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b0;
else
axi_awready <= 1'b1;
end
else
begin
/* if (!wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b0;
else
axi_awready <= 1'b1;*/
axi_awready <= 1'b0;
end
end
@@ -200,7 +210,7 @@
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID) // &&(wadr_dne))
begin
// slave is ready to accept write data when
// there is a valid write address and write data
@@ -222,7 +232,7 @@
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID; // Slave Register Write Enable
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID ; //&& (wadr_dne) ; // Slave Register Write Enable

always @( posedge S_AXI_ACLK )
begin
@@ -244,7 +254,7 @@
// Slave register 0
slv_reg0[byte_index] <= S_AXI_WDATA[(byte_index*8) +: 8];
if(byte_index <= 3) //= 4)
if(byte_index <= 3) //= 4) not need when checked with slv_reg_wren. 23022021.
s_data_done <= 1'b0; //1'b1;
else
s_data_done <= 1'b1; //1'b0;
@@ -431,7 +441,7 @@
//Enable_gen READ_ADDR_EN(.clk(S_AXI_ACLK),.rst(radr_dne),.en_in(slv_reg_rden),.en_out(read_en));
Enable_gen READ_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(radr_dne),.en_in(slv_reg_rden),.en_out(read_en));
Enable_gen WRITE_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(wadr_dne),.en_in(s_data_done),.en_out(write_en));
Enable_gen WRITE_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(wadr_dne),.en_in(s_data_done),.en_out(write_en)); //.en_in(slv_reg_wren),.en_out(write_en));
always_comb


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