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  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company:
  4. // Engineer:
  5. //
  6. // Create Date: 15.02.2021 20:04:18
  7. // Design Name:
  8. // Module Name: adderss_gen1
  9. // Project Name:
  10. // Target Devices:
  11. // Tool Versions:
  12. // Description:
  13. //
  14. // Dependencies:
  15. //
  16. // Revision:
  17. // Revision 0.01 - File Created
  18. // Additional Comments:
  19. //
  20. //////////////////////////////////////////////////////////////////////////////////
  21. module adderss_gen1(
  22. input core_clk, // input core clock.
  23. input rst_n,
  24. input en_cnt, // enable input to the counter.
  25. input [17:0]addr_in, // base or start address from Axi_slave.
  26. output reg [17:0]addrs_out, // address to the memory map
  27. output [1:0]count,
  28. output reg adr_rchd //
  29. );
  30. //wire core_clk;
  31. reg [1:0]cnt;// = 2'b11;
  32. wire [17:0] addr_out;
  33. //reg [17:0] addrs_out;
  34. //reg adr_rchd;
  35. always @ (posedge core_clk)
  36. begin
  37. if (!(rst_n && en_cnt)) // addded on 23022021.
  38. cnt <= 2'b00;
  39. else if (en_cnt)
  40. begin
  41. cnt <= cnt + 1'b1;
  42. end
  43. else
  44. // begin
  45. // if (cnt != 2'b00) // addded on 22022021.
  46. // cnt <= 2'b00; // addded on 22022021.
  47. // else // addded on 22022021.
  48. cnt <= cnt;
  49. //end
  50. end
  51. assign addr_out = {15'b0,cnt};
  52. //assign adr_rchd = (addr_out == 18'd3) ? 1'b1 : 1'b0;
  53. assign count = cnt;
  54. // assign addrs_out = (en_cnt == 1'b1) ? (addr_in |addr_out ): 18'd0;
  55. always @ (posedge core_clk)
  56. if (en_cnt)
  57. begin
  58. addrs_out <= (addr_in |addr_out );
  59. //adr_rchd <= (addr_out == 18'd3) ? 1'b1 : 1'b0;
  60. if(addr_out == 18'd3)
  61. adr_rchd <= 1'b1;
  62. else
  63. adr_rchd <= 1'b0;
  64. end
  65. else
  66. addrs_out <= 18'dZ;
  67. endmodule