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AWREADY_AWVALID v2

master
abhigna 3 years ago
parent
commit
5988bcaff5
2 changed files with 13 additions and 11 deletions
  1. +5
    -4
      sim_1/imports/sim_1/tb_axi4_Lite_MM.v
  2. +8
    -7
      sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv

+ 5
- 4
sim_1/imports/sim_1/tb_axi4_Lite_MM.v View File

@@ -113,13 +113,14 @@ module tb_axi4_Lite_MM;
// s_axi_arvalid = 0;
s_axi_aresetn = 1; // write
s_axi_awvalid = 1;
s_axi_wvalid = 1;
s_axi_awaddr = 18'h10;
s_axi_wdata = 32'h88_77_66_55; //66_55_77_88;
s_axi_wvalid = 1;
//s_axi_bready = 1;
#12
s_axi_awvalid = 0; // added on 23022021.
s_axi_wvalid = 0;
// #12
// s_axi_awvalid = 0; // added on 23022021.
// s_axi_wvalid = 0;
#12
s_axi_araddr = 18'h10;


+ 8
- 7
sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv View File

@@ -119,6 +119,8 @@
//wire we;
//wire en;
//wire [1:0]select;
reg axi_awready1; // added for aw_w_ready control signals.
reg axi_wready1; // added for aw_w_ready control signals.
reg [(C_S_AXI_DATA_WIDTH/4)-1:0] temp_slv_reg;
reg s_data_done,s_data_done_1; // Enable when all the data written in slv_reg0
wire read_en; // Enable when address is valid
@@ -160,11 +162,10 @@
// expects no outstanding transactions.
axi_awready <= 1'b1;
if (!wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b0;
else
axi_awready <= 1'b1;
/* if (!wadr_dne) // adde for control of AWready.232022021.
axi_awready <= 1'b0;
else
axi_awready <= 1'b1;*/
end
else
begin
@@ -224,7 +225,7 @@
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_AWVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
@@ -441,7 +442,7 @@
//Enable_gen READ_ADDR_EN(.clk(S_AXI_ACLK),.rst(radr_dne),.en_in(slv_reg_rden),.en_out(read_en));
Enable_gen READ_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(radr_dne),.en_in(slv_reg_rden),.en_out(read_en));
Enable_gen WRITE_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(wadr_dne),.en_in(s_data_done),.en_out(write_en)); //.en_in(slv_reg_wren),.en_out(write_en));
Enable_gen WRITE_ADDR_EN(.clk(S_AXI_ACLK),.sys_rst_n(S_AXI_ARESETN),.stop(wadr_dne),.en_in(slv_reg_wren),.en_out(write_en)); //.en_in(s_data_done),.en_out(write_en));
always_comb


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