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- `include "uvm_pkg.sv"
- import uvm_pkg ::*;
- `include "uvm_macros.svh"
- `define WIDTH 32
- `define DEPTH 64
- `define ADDR_WIDTH $clog2(`DEPTH)
-
- `include "axi_tx.sv"
- `include "axi_seq_lib.sv"
- `include "axi_sqr.sv"
- `include "axi_drv.sv"
- `include "axi_mon.sv"
- `include "axi_cov.sv"
- `include "axi_agent.sv"
- `include "axi_env.sv"
- module top;
- reg clk, rst;
- axi_intf pif(clk,rst);
- axi_env env = new();
- initial begin
- clk = 0;
- forever #5 clk = ~clk;
- end
-
- initial begin
- rst = 1;
- repeat(2) @(posedge clk);
- rst = 0;
- // #1000;
- // $finish;
- end
-
- initial begin
- run_test("axi_wr_rd_test");
- end
- //initial begin
- // $dumpvars();
- // $dumpfile("1.vcd");
- //end
-
- endmodule
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