track Files

sim_1/imports/Downloads/sc_dec_fsm_tb.sv

@@ -0,0 +1,107 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/24/2021 10:38:28 PM
+// Design Name: 
+// Module Name: sc_dec_fsm_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+`define BITS 8
+module sc_dec_fsm_tb();
+parameter N=32;
+logic clk;
+logic rst;
+logic in_valid;
+logic signed [N-1:0][`BITS-1:0]y;
+logic [N-1:0]f;
+logic [N-1:0]u_cap;
+logic [N-1:0]v_final;
+logic out_valid;
+
+task Test(input signed [`BITS-1:0] yin[N]);
+  for (int i = 0; i < N; i++)
+   y[i]=yin[i];
+  @(posedge clk);
+endtask
+
+initial
+  begin
+    rst=1'b1;
+    in_valid=1'b0;
+    y <= '{default : 0};
+    f <= '{default : 0};
+    @(posedge clk);
+    @(posedge clk);
+    in_valid=1'b1;
+    rst=1'b0;
+    
+    //Test Case for N=32
+    f <= '{1,1,1,1,1,1,1,0,1,1,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+    Test('{-7'd1,-7'd1,7'd1,7'd1,7'd1,-7'd1,7'd1,7'd1,7'd1,7'd1,-7'd1,7'd1,-7'd1,-7'd1,-7'd1,-7'd1,-7'd1,-7'd1,-7'd1,-7'd1,-7'd1,7'd1,7'd1,7'd1,7'd1,7'd1,7'd1,-7'd1,7'd1,7'd1,-7'd1,-7'd1});
+    
+    //Test Case for N=16
+//    f <= '{1,1,1,1,1,0,0,0,1,0,0,0,0,0,0,0};
+//    Test('{ -7'd1,-7'd1,-7'd1,7'd1,7'd1,-7'd1,7'd1,7'd1,-7'd1,7'd1,7'd1,7'd1,7'd1,7'd1,-7'd1,7'd1});
+    
+    //Test Case for N=8
+  // f<='{1,1,1,0,1,0,0,0};
+  //   f<='{0,0,0,1,0,1,1,1};
+  //  Test('{ -7'd1,7'd1, -7'd1, 7'd1,7'd1,-7'd1, 7'd1, -7'd1});
+    
+    //Test Cases for N=4
+//    f <= '{1, 1, 0, 0};
+//   Test('{ 7'd1,-7'd3, 7'd2, -7'd1});
+ //   #650; 
+ //   f <= '{0, 0, 0, 0};
+ //   Test('{ -7'd2,7'd1, -7'd1, -7'd2});
+    
+ /*    f <= '{1, 1, 0, 0};
+     Test('{ -7'd2,7'd1, -7'd1, -7'd2});
+     
+    //Test Case for N=2
+     f<='{0,0};
+     Test('{ 7'd0,7'd1});
+   
+     f<='{0,0};
+     Test('{ -7'd1,7'd1});
+     
+     f<='{0,1};
+     Test('{ -7'd2,7'd1});
+     
+     f<='{1,1};
+     Test('{ -7'd2,7'd1});*/
+   #50000;
+    $stop;
+  end
+  
+initial
+  begin
+    clk = 0;
+    forever #2.03 clk = ~clk;
+  end
+
+sc_decoder_fsm #(.N(N)) sc_dec_fsm
+(
+.clk(clk),
+.rst(rst),
+.in_valid(in_valid),
+.y(y),
+.f(f),
+.u_cap(u_cap),
+.v_final(v_final),
+.out_valid(out_valid)
+);
+
+endmodule

sources_1/imports/Downloads/bram.sv

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/03/2021 12:49:56 PM
+// Design Name: 
+// Module Name: bram
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module bram_v #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256)(
+input wire clk,ena,enb,wea,
+input wire [ADDR_WIDTH-1:0]addra, addrb,
+input wire [DATA_WIDTH-1:0]dia,
+output reg [DATA_WIDTH-1:0]dob
+);
+(*ram_style="block"*)reg [DATA_WIDTH-1:0]ram[0:DEPTH-1];
+always@(posedge clk) 
+    begin
+    if (ena) 
+        begin
+        if (wea)
+        ram[addra] <=dia;
+        end
+    end
+always @(posedge clk) 
+    begin
+   if (enb) 
+        dob <= ram[addrb];
+    end
+endmodule   
+

sources_1/imports/Downloads/bram_L.sv

@@ -0,0 +1,44 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/09/2021 12:54:48 AM
+// Design Name: 
+// Module Name: bram_L
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module bram_L #(parameter BITS=8, ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256, N=4)(
+input wire clk,ena,enb,wea,
+input wire [ADDR_WIDTH-1:0]addra, addrb,
+//input wire [N-1:0][7:0]dia,
+//output reg [N-1:0][7:0]dob
+input wire [(N*BITS-1):0]dia,
+output reg [(N*BITS-1):0]dob
+);
+(*ram_style="block"*)reg [DATA_WIDTH-1:0]ram[0:DEPTH-1];
+always@(posedge clk) 
+    begin
+    if (ena) 
+        begin
+        if (wea)
+        ram[addra] <=dia;
+        end
+    end
+always @(posedge clk) 
+    begin
+   if (enb) 
+        dob <= ram[addrb];
+    end
+endmodule   
+