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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company:
- // Engineer:
- //
- // Create Date: 03/09/2021 12:54:48 AM
- // Design Name:
- // Module Name: bram_L
- // Project Name:
- // Target Devices:
- // Tool Versions:
- // Description:
- //
- // Dependencies:
- //
- // Revision:
- // Revision 0.01 - File Created
- // Additional Comments:
- //
- //////////////////////////////////////////////////////////////////////////////////
- module bram_L #(parameter BITS=8, ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256, N=4)(
- input wire clk,ena,enb,wea,
- input wire [ADDR_WIDTH-1:0]addra, addrb,
- //input wire [N-1:0][7:0]dia,
- //output reg [N-1:0][7:0]dob
- input wire [(N*BITS-1):0]dia,
- output reg [(N*BITS-1):0]dob
- );
- (*ram_style="block"*)reg [DATA_WIDTH-1:0]ram[0:DEPTH-1];
- always@(posedge clk)
- begin
- if (ena)
- begin
- if (wea)
- ram[addra] <=dia;
- end
- end
- always @(posedge clk)
- begin
- if (enb)
- dob <= ram[addrb];
- end
- endmodule
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