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sc_decoder_fsm.sv 31 KiB

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  1. `timescale 1ns/1ps
  2. `define BITS 8
  3. module sc_decoder_fsm #(parameter BITS=8, N=11'd128)(
  4. input clk, rst,
  5. input in_valid,
  6. input signed [N-1:0][BITS-1:0] y,
  7. input [N-1:0] f,
  8. output wire [N-1:0] u_cap,
  9. output wire [N-1:0] v_final,
  10. output wire out_valid
  11. );
  12. //function for fminsum calculation
  13. function void fminsum_calc;
  14. input signed [`BITS-1:0] a;
  15. input signed [`BITS-1:0] b;
  16. output signed [`BITS-1:0] c;
  17. logic [`BITS-2:0] abs_a;
  18. logic [`BITS-2:0] abs_b;
  19. logic [`BITS-2:0] abs_c;
  20. abs_a = (a[`BITS-1]) ? ~a[`BITS-2:0] + 1'b1 : a[`BITS-2:0];
  21. abs_b = (b[`BITS-1]) ? ~b[`BITS-2:0] + 1'b1 : b[`BITS-2:0];
  22. abs_c = (abs_b < abs_a) ? abs_b : abs_a;
  23. c[`BITS-1] = a[`BITS-1] ^ b[`BITS-1];
  24. c[`BITS-2:0] = (c[`BITS-1]) ? ~abs_c + 1'b1 : abs_c;
  25. endfunction
  26. //function for g-value calculation
  27. function void g_calc;
  28. input signed [`BITS-1:0] a;
  29. input signed [`BITS-1:0] b;
  30. input u;
  31. output signed [`BITS:0] c;
  32. c = (u == 0) ? (b + a) : (b + (~a+1'b1));
  33. endfunction
  34. // Parameter
  35. localparam d = $clog2(N);
  36. // Internal Signals
  37. logic [N-1:0][BITS-1:0] L_in = 'b0, L_out;
  38. logic [d :0] temp_index_f,temp_index_g;
  39. logic [N-1:0] v_in, v_out;
  40. logic [11 :0] jL1,jL2,
  41. jU1,jU2,
  42. jR1,jR2,jR3;
  43. logic ena_v,enb_v,wea_v;
  44. logic ena_L,enb_L,wea_L;
  45. logic [N-1:0]u;
  46. reg signed [BITS-1:0] LRU[2];
  47. reg [N-1:0]v;
  48. // State Variables
  49. logic [4:0] c_state, n_state;
  50. //Auxiliary registers declarations
  51. logic [d:0] depth = 'b0,depth_reg;
  52. logic [d:0] node = 'b0,node_reg;
  53. logic [11:0] tmp_L, tmp_L_reg,
  54. tmp_R, tmp_R_reg,
  55. tmp_U, tmp_U_reg;
  56. //FSM States
  57. localparam idle = 5'd0 , root = 5'd1 , wait_L_logic = 5'd2,
  58. wait_L = 5'd3 , state_L = 5'd4 , wait_R_logic = 5'd5,
  59. wait_R = 5'd6 , state_R = 5'd7 , wait_U_logic = 5'd8,
  60. wait_U = 5'd9 , state_U = 5'd10, wait_LRU_logic = 5'd11,
  61. wait_LRU = 5'd12, state_LRU = 5'd13, wait_lnode_logic = 5'd14,
  62. wait_lnode = 5'd15, state_lnode = 5'd16, wait_lstate_logic = 5'd17,
  63. wait_lstate = 5'd18, state_last = 5'd19;
  64. //BlockRAM Instantiations
  65. bram_v #( .ADDR_WIDTH(d-1),
  66. .DATA_WIDTH(N),
  67. .DEPTH(2**(d-1)))
  68. bram_v_i (
  69. .clk(clk),.ena(ena_v),.enb(enb_v),
  70. .addra(depth_reg-1'b1),
  71. .addrb(depth_reg),
  72. .wea(wea_v),
  73. .dia(v_in),
  74. .dob(v_out));
  75. bram_L #( .ADDR_WIDTH(d-1),
  76. .DATA_WIDTH(N*BITS),
  77. .DEPTH(2**(d-1)),
  78. .N(N))
  79. bram_L_i (
  80. .clk(clk),.ena(ena_L),.enb(enb_L),
  81. .addra(depth_reg),
  82. .addrb(depth_reg-1'b1),
  83. .wea(wea_L),
  84. .dia(L_in),
  85. .dob(L_out));
  86. //output assignment
  87. for(genvar i=0; i<N; i++)
  88. assign u_cap[i] = u[i];
  89. assign v_final = v;
  90. assign out_valid = (n_state == state_lnode) ? 1'b1 : 1'b0;
  91. // Sequential Logic - FSM State and Data Registers
  92. always_ff@(posedge clk)
  93. begin
  94. if(rst)
  95. begin
  96. c_state <= idle;
  97. depth_reg <= 0;
  98. node_reg <= 0;
  99. tmp_L_reg <= 0;
  100. tmp_R_reg <= 0;
  101. tmp_U_reg <= 0;
  102. end
  103. else
  104. begin
  105. c_state <= n_state;
  106. depth_reg <= depth;
  107. node_reg <= node;
  108. tmp_L_reg <= tmp_L;
  109. tmp_R_reg <= tmp_R;
  110. tmp_U_reg <= tmp_U;
  111. end
  112. end
  113. //Combinational Logic - FSM Next State Logic
  114. always_comb
  115. begin
  116. u = 0;
  117. v = 0;
  118. tmp_L = 0; tmp_R = 0; tmp_U = 0;
  119. ena_L = 0; enb_L = 0;
  120. wea_L = 0;
  121. node = node_reg;
  122. depth = depth_reg;
  123. // L_in = L_in;
  124. if(in_valid)
  125. case(c_state)
  126. idle:
  127. begin
  128. // L_in = 0;
  129. depth = 0; node = 0;
  130. tmp_L = 0; tmp_R = 0; tmp_U = 0;
  131. ena_L = 0; wea_L = 0; enb_L = 0;
  132. ena_v = 0; wea_v = 0; enb_v = 0;
  133. u = 0; v = 0;
  134. if(out_valid)
  135. n_state = idle;
  136. else
  137. n_state = root;
  138. end
  139. root:
  140. begin
  141. depth = depth_reg;
  142. node = node_reg;
  143. ena_L = 1'b1; wea_L = 1'b1;
  144. enb_L = 0; ena_v = 0;
  145. wea_v = 0; enb_v = 0;
  146. tmp_L = tmp_L_reg;
  147. tmp_R = tmp_R_reg;
  148. tmp_U = tmp_U_reg;
  149. u = u;
  150. v = v;
  151. for(int k = 0; k < N; k++)
  152. L_in[k] = y[k];
  153. // L_in = y;
  154. n_state = wait_L_logic;
  155. end
  156. wait_L_logic:
  157. begin
  158. // L_in = L_in;
  159. depth = depth_reg + 1'b1; node = ((2*node_reg) + 1'b1);
  160. ena_L = 0; wea_L = 0;
  161. tmp_L = 0; enb_L = 1'b1;
  162. ena_v = 0; wea_v = 0;
  163. enb_v = 0;
  164. tmp_R = tmp_R_reg;
  165. tmp_U = tmp_U_reg;
  166. u = u;
  167. v = v;
  168. if(depth < d)
  169. n_state = wait_L;
  170. else
  171. n_state = wait_LRU_logic;
  172. end
  173. wait_L:
  174. begin
  175. u = u;
  176. v = v;
  177. // L_in = L_in;
  178. tmp_L = tmp_L_reg;
  179. tmp_R = tmp_R_reg;
  180. tmp_U = tmp_U_reg;
  181. ena_L = ena_L; enb_L = enb_L;
  182. wea_L = wea_L;
  183. // depth = depth_reg;
  184. n_state = state_L;
  185. end
  186. state_L:
  187. begin
  188. u = u;
  189. v = v;
  190. // depth = depth_reg;
  191. ena_L = 1'b1; wea_L = 1'b1; enb_L = 0;
  192. ena_v = 0; wea_v = 0; enb_v = 0;
  193. tmp_L = tmp_L_reg + 1'b1;
  194. tmp_R = tmp_R_reg;
  195. tmp_U = tmp_U_reg;
  196. temp_index_f = ((N/(2**(depth+1'b1))) * ((2*(node) + 1'b1) - ((2**(depth + 1'b1)) - 1'b1)));
  197. jL1 = (tmp_L_reg) + temp_index_f;
  198. jL2 = (tmp_L_reg) + temp_index_f + (N/(2**depth));
  199. fminsum_calc(L_out[jL1],L_out[jL2],L_in[jL1]);
  200. if(tmp_L< (N/(2**depth)))
  201. n_state = state_L;
  202. else if(depth < d)
  203. n_state = wait_L_logic;
  204. else
  205. n_state = wait_LRU_logic;
  206. end
  207. wait_R_logic:
  208. begin
  209. u = u;
  210. v = v;
  211. // L_in = L_in;
  212. ena_L = ena_L; enb_L = enb_L;
  213. wea_L = wea_L;
  214. depth = depth_reg - 1'b1;
  215. node = node_reg + 1'b1;
  216. tmp_L = tmp_L_reg;
  217. tmp_U = tmp_U_reg;
  218. tmp_R = 0;
  219. n_state = wait_R;
  220. end
  221. wait_R:
  222. begin
  223. // depth = depth_reg;
  224. // L_in = L_in;
  225. ena_L = 0;wea_L = 0; enb_L = 1'b1;
  226. ena_v = 0;wea_v = 0; enb_v = 1'b1;
  227. wea_L = wea_L;
  228. u = u;
  229. v = v;
  230. tmp_L = tmp_L_reg;
  231. tmp_R = tmp_R_reg;
  232. tmp_U = tmp_U_reg;
  233. n_state = state_R;
  234. end
  235. state_R:
  236. begin
  237. // depth = depth_reg;
  238. u = u;
  239. v = v;
  240. ena_L = 1'b1; wea_L = 1'b1; enb_L = 0;
  241. ena_v = 0; wea_v = 0; enb_v = 0;
  242. tmp_L = tmp_L_reg;
  243. tmp_U = tmp_U_reg;
  244. tmp_R = tmp_R_reg + 1'b1;
  245. temp_index_f = ((N/(2**(depth + 1'b1))) * ((2*(node) + 1'b1) -((2**(depth + 1'b1)) - 1'b1)));
  246. temp_index_g = ((N/(2**(depth + 1'b1))) * ((2*(node - 1'b1) + 1'b1)-((2**(depth + 1'b1)) - 1'b1)));
  247. jR1 = (tmp_R_reg) + temp_index_g;
  248. jR2 = (tmp_R_reg) + temp_index_g + (N/(2**depth));
  249. jR3 = (tmp_R_reg) + temp_index_f;
  250. g_calc(L_out[jR1],L_out[jR2],v_out[jR1],L_in[jR3]);
  251. if(tmp_R < (N/(2**depth)))
  252. n_state = state_R;
  253. else if(node == ((2**d) - 2))
  254. n_state = wait_lnode_logic;
  255. else if(depth == d)
  256. n_state = wait_LRU_logic;
  257. else
  258. n_state = wait_L_logic;
  259. end
  260. wait_U_logic:
  261. begin
  262. depth = depth_reg - 1'b1;
  263. node = (node_reg - 2) >> 1;
  264. // L_in = L_in;
  265. tmp_U = 0;
  266. wea_L = wea_L;
  267. u = u;
  268. v = v;
  269. ena_L = ena_L; enb_L = enb_L;
  270. tmp_L = tmp_L_reg;
  271. tmp_R = tmp_R_reg;
  272. n_state = wait_U;
  273. end
  274. wait_U:
  275. begin
  276. // depth = depth_reg;
  277. // L_in = L_in;
  278. ena_L = 0; wea_L = 0; enb_L = 0;
  279. ena_v = 0; wea_v = 0; enb_v = 1'b1;
  280. tmp_L = tmp_L_reg;
  281. tmp_R = tmp_R_reg;
  282. tmp_U = tmp_U_reg;
  283. n_state = state_U;
  284. end
  285. state_U:
  286. begin
  287. // depth = depth_reg;
  288. // L_in = L_in;
  289. ena_L = 0; ena_v =1'b1; enb_L = 0;
  290. wea_L = 0; wea_v =1'b1; enb_v = 0;
  291. u = u;
  292. v = v;
  293. tmp_L = tmp_L_reg;
  294. tmp_R = tmp_R_reg;
  295. tmp_U = tmp_U_reg+1'b1;
  296. temp_index_f = ((N/(2**(depth))) * ((2*node + 1'b1) - ((2**(depth)) - 1'b1)));
  297. jU1 = (tmp_U_reg) + temp_index_f;
  298. jU2 = (tmp_U_reg) + temp_index_f + (N/(2**(depth)));
  299. v_in[jU1] = v_out[jU1] ^ v_out[jU2];
  300. v_in[jU2] = v_out[jU2];
  301. if(tmp_U < (N/(2**(depth))))
  302. n_state = state_U;
  303. else if(depth > 0 && ~node[0])
  304. n_state = wait_U_logic;
  305. else if(depth > 0 && node!=0)
  306. n_state = wait_R_logic;
  307. else
  308. n_state = wait_lstate_logic;
  309. end
  310. wait_LRU_logic:
  311. begin
  312. u = u;
  313. v = v;
  314. // L_in = L_in;
  315. wea_L = wea_L;
  316. // depth = depth_reg;
  317. tmp_L = tmp_L_reg;
  318. tmp_R = tmp_R_reg;
  319. tmp_U = tmp_U_reg;
  320. ena_L = ena_L; enb_L = enb_L;
  321. node = (node_reg - 1'b1) >> 1;
  322. n_state = wait_LRU;
  323. end
  324. wait_LRU:
  325. begin
  326. // depth = depth_reg;
  327. // L_in = L_in;
  328. u = u;
  329. v = v;
  330. ena_L = 0; wea_L = 0; enb_L = 1'b1;
  331. ena_v = 0; wea_v = 0; enb_v = 0;
  332. tmp_L = tmp_L_reg;
  333. tmp_R = tmp_R_reg;
  334. tmp_U = tmp_U_reg;
  335. n_state = state_LRU;
  336. end
  337. state_LRU:
  338. begin
  339. // depth = depth_reg;
  340. ena_L = 0; ena_v = 1'b1;
  341. enb_v = 0; wea_v = 1'b1;
  342. wea_L = 0; enb_L = 0;
  343. // L_in = L_in;
  344. v = v;
  345. tmp_L = tmp_L_reg;
  346. tmp_R = tmp_R_reg;
  347. tmp_U = tmp_U_reg;
  348. temp_index_f = ((N/(2**(depth))) * ((2*node + 1'b1) - ((2**(depth)) - 1'b1)));
  349. fminsum_calc(L_out[temp_index_f],L_out[temp_index_f + 1],LRU[0]);
  350. u[(2*node)+2-N] = (f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1 : 0);
  351. g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);
  352. u[(2*node)+3-N] = (f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1 : 0);
  353. v_in[temp_index_f] = u[(2*node)+2-N] ^ u[(2*node)+3-N];
  354. v_in[temp_index_f+1] = u[(2*node)+3-N];
  355. if(node[0])
  356. n_state = wait_R_logic;
  357. else
  358. n_state = wait_U_logic;
  359. end
  360. wait_lnode_logic:
  361. begin
  362. u = u;
  363. v = v;
  364. // L_in = L_in;
  365. tmp_L = tmp_L_reg;
  366. tmp_R = tmp_R_reg;
  367. tmp_U = tmp_U_reg;
  368. depth = depth_reg + 1'b1; node = node_reg;
  369. ena_L = ena_L; enb_L = enb_L;
  370. wea_L = wea_L;
  371. n_state = wait_lnode;
  372. end
  373. wait_lnode:
  374. begin
  375. // depth = depth_reg;
  376. u = u;
  377. v = v;
  378. tmp_L = tmp_L_reg;
  379. tmp_R = tmp_R_reg;
  380. tmp_U = tmp_U_reg;
  381. // L_in = L_in;
  382. ena_L = 0; wea_L = 0; enb_L = 1'b1;
  383. ena_v = 0; wea_v = 0; enb_v = 0;
  384. n_state = state_lnode;
  385. end
  386. state_lnode:
  387. begin
  388. // depth = depth_reg;
  389. u = u;
  390. v = v;
  391. // L_in = L_in;
  392. ena_L = 0; wea_L = 0; enb_L = 0;
  393. ena_v = 1'b1; wea_v = 1'b1; enb_v = 0;
  394. tmp_L = tmp_L_reg;
  395. tmp_R = tmp_R_reg;
  396. tmp_U = tmp_U_reg;
  397. temp_index_f = ((N/(2**(depth))) * ((2*node + 1'b1) - ((2**(depth)) - 1'b1)));
  398. fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);
  399. u[(2*node)+2-N] = (f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1'b1 : 0);
  400. g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);
  401. u[(2*node)+3-N] = (f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1'b1 : 0);
  402. v_in[temp_index_f] = u[(2*node)+2-N] ^ u[(2*node)+3-N];
  403. v_in[temp_index_f+1] = u[(2*node)+3-N];
  404. n_state = wait_U_logic;
  405. end
  406. wait_lstate_logic:
  407. begin
  408. u = u;
  409. v = v;
  410. // L_in = L_in;
  411. // depth = depth_reg;
  412. node = node_reg;
  413. tmp_L = tmp_L_reg;
  414. tmp_R = tmp_R_reg;
  415. tmp_U = tmp_U_reg;
  416. ena_L = ena_L; enb_L = enb_L;
  417. wea_L = wea_L;
  418. n_state = wait_lstate;
  419. end
  420. wait_lstate:
  421. begin
  422. // depth = depth_reg;
  423. u = u;
  424. v = v;
  425. // L_in = L_in;
  426. ena_L = 0; wea_L = 0; enb_L = 1'b1;
  427. ena_v = 0; wea_v = 0; enb_v = 0;
  428. tmp_L = tmp_L_reg;
  429. tmp_R = tmp_R_reg;
  430. tmp_U = tmp_U_reg;
  431. n_state = state_last;
  432. end
  433. state_last:
  434. begin
  435. // depth = depth_reg;
  436. // L_in = L_in;
  437. u = u;
  438. ena_L = 0; wea_L = 0; enb_L = 0;
  439. ena_v = 1'b1; wea_v = 1'b1; enb_v = 0;
  440. tmp_L = tmp_L_reg;
  441. tmp_R = tmp_R_reg;
  442. tmp_U = tmp_U_reg;
  443. v = v_out;
  444. n_state = idle;
  445. end
  446. default:
  447. begin
  448. u = 0;
  449. v = 0;
  450. // L_in = 0;
  451. depth = 0; node = 0;
  452. tmp_L = 0; tmp_R = 0; tmp_U = 0;
  453. ena_L = 0; enb_L = 0; wea_L = 0;
  454. ena_v = 0; wea_v = 0; enb_v = 0;
  455. n_state = idle;
  456. end
  457. endcase
  458. else
  459. begin
  460. u = 0;
  461. v = 0;
  462. // L_in = 0;
  463. depth = 0; node = 0;
  464. tmp_L = 0; tmp_R = 0; tmp_U = 0;
  465. ena_L = 0; wea_L = 0; enb_L = 0;
  466. ena_v = 0; wea_v = 0; enb_v = 0;
  467. n_state = idle;
  468. end
  469. end
  470. endmodule
  471. /*
  472. `timescale 1ns / 1ns
  473. //////////////////////////////////////////////////////////////////////////////////
  474. // Company:
  475. // Engineer:
  476. //
  477. // Create Date: 02/24/2021 08:03:07 PM
  478. // Design Name:
  479. // Module Name: sc_decoder_fsm
  480. // Project Name:
  481. // Target Devices:
  482. // Tool Versions:
  483. // Description:
  484. //
  485. // Dependencies:
  486. //
  487. // Revision:
  488. // Revision 0.01 - File Created
  489. // Additional Comments:
  490. //
  491. //////////////////////////////////////////////////////////////////////////////////
  492. `define BITS 8
  493. module sc_decoder_fsm #(parameter BITS=8, N=11'd16)(
  494. input clk, rst,
  495. input in_valid,
  496. input signed [BITS-1:0] y[N],
  497. input f[N],
  498. output wire u_cap[N],
  499. output wire [N-1:0]v_final,
  500. output wire out_valid
  501. );
  502. //function for fminsum calculation
  503. function void fminsum_calc;
  504. input signed [`BITS-1:0] a;
  505. input signed [`BITS-1:0] b;
  506. output signed [`BITS-1:0] c;
  507. logic [`BITS-2:0] abs_a;
  508. logic [`BITS-2:0] abs_b;
  509. logic [`BITS-2:0] abs_c;
  510. abs_a = (a[`BITS-1] == 1) ? ~a[`BITS-2:0] + 1 : a[`BITS-2:0];
  511. abs_b = (b[`BITS-1] == 1) ? ~b[`BITS-2:0] + 1 : b[`BITS-2:0];
  512. c[`BITS-1] = a[`BITS-1] ^ b[`BITS-1];
  513. abs_c = (abs_b < abs_a) ? abs_b : abs_a;
  514. c[`BITS-2:0] = (c[`BITS-1] == 1) ? ~abs_c + 1 : abs_c;
  515. endfunction
  516. //function for g-value calculation
  517. function void g_calc;
  518. input signed [`BITS-1:0] a;
  519. input signed [`BITS-1:0] b;
  520. input u;
  521. output signed [`BITS:0] c;
  522. c = (u == 0) ? (b + a) : (b + (~a+1));
  523. endfunction
  524. //parameters and signals declarations
  525. localparam d=$clog2(N); //N=4, d=2(0 & 1)
  526. localparam n=2*N-1; //(2**d)-1;
  527. localparam cmax=0;
  528. logic u[N];
  529. logic [d:0]temp_index_f,temp_index_g;
  530. reg signed [BITS-1:0] LRU[2];
  531. reg [N-1:0]v;
  532. logic [N-1:0][BITS-1:0]L_in, L_out;
  533. logic [N-1:0]v_in, v_out;
  534. logic ena_v,enb_v,wea_v;
  535. logic ena_L,enb_L,wea_L;
  536. logic [1:0]counter,counter_reg;
  537. logic [11:0]jL1,jL2,jR1,jR2,jR3,jU1,jU2;
  538. logic [4:0] c_state, n_state;
  539. //Auxiliary registers declarations
  540. logic [d:0] depth,depth_reg;
  541. logic [d:0] node,node_reg;
  542. logic [11:0]tmp_L,tmp_L_reg, tmp_R,tmp_R_reg,tmp_U, tmp_U_reg;
  543. //FSM States
  544. localparam idle=5'd0, root=5'd1, wait_L_logic=5'd2, wait_L=5'd3, state_L=5'd4, wait_R_logic=5'd5, wait_R=5'd6, state_R=5'd7;
  545. localparam wait_U_logic=5'd8, wait_U=5'd9, state_U=5'd10,wait_LRU_logic=5'd11, wait_LRU=5'd12, state_LRU=5'd13;
  546. localparam wait_lnode_logic=5'd14, wait_lnode=5'd15, state_lnode=5'd16,wait_lstate_logic=5'd17, wait_lstate=5'd18, state_last=5'd19;
  547. //BlockRAM Instantiations
  548. bram_v #(.ADDR_WIDTH(d-1),.DATA_WIDTH(N),.DEPTH(2**(d-1))) bram_v_i (
  549. .clk(clk),.ena(ena_v),.enb(enb_v),
  550. .addra(depth_reg-1),
  551. .addrb(depth_reg),
  552. .wea(wea_v),
  553. .dia(v_in),
  554. .dob(v_out)
  555. );
  556. bram_L #(.ADDR_WIDTH(d-1),.DATA_WIDTH(N*BITS),.DEPTH(2**(d-1)),.N(N)) bram_L_i (
  557. .clk(clk),.ena(ena_L),.enb(enb_L),
  558. .addra(depth_reg),
  559. .addrb(depth_reg-1),
  560. .wea(wea_L),
  561. .dia(L_in),
  562. .dob(L_out)
  563. );
  564. //output assignment
  565. for(genvar i=0; i<N; i++)
  566. begin
  567. assign u_cap[i] = u[i];
  568. end
  569. assign v_final=v;
  570. assign out_valid=(n_state==state_last)?1'b1:1'b0;
  571. // Sequential Logic - FSM State and Data Registers
  572. always_ff@(posedge clk)
  573. begin
  574. if(rst==1)
  575. begin
  576. c_state <= idle;
  577. depth_reg<=0;
  578. node_reg<=0;
  579. counter_reg<=0;
  580. tmp_L_reg<=0;
  581. tmp_R_reg<=0;
  582. tmp_U_reg<=0;
  583. end
  584. else
  585. begin
  586. c_state <= n_state;
  587. depth_reg<=depth;
  588. node_reg<=node;
  589. counter_reg<=counter;
  590. tmp_L_reg<=tmp_L;
  591. tmp_R_reg<=tmp_R;
  592. tmp_U_reg<=tmp_U;
  593. end
  594. end
  595. //Combinational Logic - FSM Next State Logic
  596. always_comb
  597. //always@(y or c_state or f, L_out)
  598. begin
  599. if(in_valid==1)
  600. case(c_state)
  601. idle: begin
  602. depth=0; node=0; counter=0; tmp_L=0; tmp_R=0; tmp_U=0;
  603. ena_L=0;wea_L=0;enb_L=0;
  604. ena_v=0;wea_v=0; enb_v=0;
  605. if(out_valid==1)
  606. n_state=idle;
  607. else
  608. n_state=root;
  609. end
  610. root: begin
  611. depth=depth_reg;node=node_reg;
  612. ena_L=1;wea_L=1;enb_L=0;
  613. ena_v=0;wea_v=0; enb_v=0;
  614. for(int k=0; k<N; k++)
  615. L_in[k]=y[k];
  616. n_state=wait_L_logic;
  617. end
  618. wait_L_logic:
  619. begin
  620. depth=depth_reg+1; node=((2*node_reg)+1); tmp_L=0;
  621. ena_L=0;wea_L=0;enb_L=1;
  622. ena_v=0;wea_v=0; enb_v=0;
  623. if(depth < d)
  624. n_state = wait_L;
  625. else
  626. n_state = wait_LRU_logic;
  627. end
  628. wait_L: begin
  629. if(counter==cmax) begin
  630. counter=counter_reg-cmax;
  631. n_state=state_L;
  632. end
  633. else
  634. counter=counter_reg+1;
  635. end
  636. state_L: begin
  637. ena_L=1;wea_L=1;enb_L=0;
  638. ena_v=0;wea_v=0; enb_v=0;
  639. tmp_L=tmp_L_reg+1;
  640. temp_index_f=((N/(2**(depth+1)))*((2*(node)+1)-((2**(depth+1))-1)));
  641. jL1=(tmp_L_reg)+temp_index_f;
  642. jL2=(tmp_L_reg)+temp_index_f+(N/(2**depth));
  643. fminsum_calc(L_out[jL1],L_out[jL2],L_in[jL1]);
  644. if(tmp_L< (N/(2**depth)))
  645. n_state=state_L;
  646. else if(depth<d)
  647. n_state=wait_L_logic;
  648. else
  649. n_state=wait_LRU_logic;
  650. end
  651. wait_R_logic: begin
  652. depth=depth_reg-1; node=node_reg+1; tmp_R=0;
  653. n_state=wait_R;
  654. end
  655. wait_R: begin
  656. ena_L=0;wea_L=0;enb_L=1;
  657. ena_v=0;wea_v=0; enb_v=1;
  658. if(counter==cmax) begin
  659. counter=counter_reg-cmax;
  660. n_state=state_R;
  661. end
  662. else
  663. counter=counter_reg+1;
  664. end
  665. state_R: begin
  666. ena_L=1;wea_L=1;enb_L=0;
  667. ena_v=0;wea_v=0; enb_v=0;
  668. tmp_R=tmp_R_reg+1;
  669. temp_index_f=((N/(2**(depth+1)))*((2*(node)+1)-((2**(depth+1))-1)));
  670. temp_index_g=((N/(2**(depth+1)))*((2*(node-1)+1)-((2**(depth+1))-1)));
  671. jR1=(tmp_R_reg)+temp_index_g;
  672. jR2=(tmp_R_reg)+temp_index_g+(N/(2**depth));
  673. jR3=(tmp_R_reg)+temp_index_f;
  674. g_calc(L_out[jR1],L_out[jR2],v_out[jR1],L_in[jR3]);
  675. if(tmp_R< (N/(2**depth)))
  676. n_state=state_R;
  677. else if(node==((2**d)-2))
  678. n_state=wait_lnode_logic;
  679. else if(depth==d)
  680. n_state=wait_LRU_logic;
  681. else
  682. n_state = wait_L_logic;
  683. end
  684. wait_U_logic: begin
  685. depth=depth_reg-1; node=(node_reg-2)/2; tmp_U=0;
  686. n_state=wait_U;
  687. end
  688. wait_U: begin
  689. ena_L=0;wea_L=0;enb_L=0;
  690. ena_v=0;wea_v=0; enb_v=1;
  691. if(counter==cmax) begin
  692. counter=counter_reg-cmax;
  693. n_state=state_U;
  694. end
  695. else
  696. counter=counter_reg+1;
  697. end
  698. state_U: begin
  699. ena_L=0;wea_L=0;enb_L=0;
  700. ena_v=1;wea_v=1; enb_v=0;
  701. tmp_U=tmp_U_reg+1;
  702. temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1)));
  703. jU1=(tmp_U_reg)+temp_index_f;
  704. jU2=(tmp_U_reg)+temp_index_f+(N/(2**(depth)));
  705. v_in[jU1] = v_out[jU1] ^ v_out[jU2];
  706. v_in[jU2] = v_out[jU2];
  707. if(tmp_U<(N/(2**(depth))))
  708. n_state=state_U;
  709. else if(depth>0 && node%2==0)
  710. n_state = wait_U_logic;
  711. else if(depth>0 && node!=0)
  712. n_state=wait_R_logic;
  713. else
  714. n_state=wait_lstate_logic;
  715. end
  716. wait_LRU_logic: begin
  717. depth=depth_reg; node=(node_reg-1)/2;
  718. n_state=wait_LRU;
  719. end
  720. wait_LRU: begin
  721. ena_L=0;wea_L=0;enb_L=1;
  722. ena_v=0;wea_v=0; enb_v=0;
  723. if(counter==cmax) begin
  724. counter=counter_reg-cmax;
  725. n_state=state_LRU;
  726. end
  727. else
  728. counter=counter_reg+1;
  729. end
  730. state_LRU: begin
  731. ena_L=0;wea_L=0;enb_L=0;
  732. ena_v=1;wea_v=1; enb_v=0;
  733. temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1)));
  734. fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);
  735. u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0);
  736. g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);
  737. u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0);
  738. v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N];
  739. v_in[temp_index_f+1]=u[(2*node)+3-N];
  740. if(node%2==1)
  741. n_state = wait_R_logic;
  742. else
  743. n_state=wait_U_logic;
  744. end
  745. wait_lnode_logic: begin
  746. depth=depth_reg+1; node=node_reg;
  747. n_state=wait_lnode;
  748. end
  749. wait_lnode: begin
  750. ena_L=0;wea_L=0;enb_L=1;
  751. ena_v=0;wea_v=0; enb_v=0;
  752. if(counter==cmax) begin
  753. counter=counter_reg-cmax;
  754. n_state=state_lnode;
  755. end
  756. else
  757. counter=counter_reg+1;
  758. end
  759. state_lnode: begin
  760. ena_L=0;wea_L=0;enb_L=0;
  761. ena_v=1;wea_v=1; enb_v=0;
  762. temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1)));
  763. fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);
  764. u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0);
  765. g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);
  766. u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0);
  767. v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N];
  768. v_in[temp_index_f+1]=u[(2*node)+3-N];
  769. n_state = wait_U_logic;
  770. end
  771. wait_lstate_logic: begin
  772. depth=depth_reg; node=node_reg;
  773. n_state=wait_lstate;
  774. end
  775. wait_lstate: begin
  776. ena_L=0;wea_L=0;enb_L=1;
  777. ena_v=0;wea_v=0; enb_v=0;
  778. if(counter==cmax) begin
  779. counter=counter_reg-cmax;
  780. n_state=state_last;
  781. end
  782. else
  783. counter=counter_reg+1;
  784. end
  785. state_last: begin
  786. ena_L=0;wea_L=0;enb_L=0;
  787. ena_v=1;wea_v=1; enb_v=0;
  788. v=v_out;
  789. n_state=idle;
  790. end
  791. endcase
  792. else n_state = idle;
  793. end
  794. endmodule
  795. */