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@@ -8,24 +8,41 @@ module crc_gen #( |
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)( |
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input clk_i, |
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input rst_n, |
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input [24:0] POLY, |
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input [DATA_WIDTH - 1 : 0] data_i, // Input Information bit |
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output reg [CRC_SIZE - 1 : 0] crc_o // output CRC of information Input |
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// input [24:0] POLY, |
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input [7:0] a_in, // Number of valid bits on input |
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input [7:0] k_in, // Number of valid bits on output |
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input [DATA_WIDTH - 1 : 0] data_i, // Input Information bit |
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output reg [CRC_SIZE - 1 : 0] crc_o // output CRC of information Input |
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); |
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logic [CRC_SIZE - 1 : 0] crc = 0; |
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logic [CRC_SIZE - 1 : 0] crc_next; |
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logic [CRC_SIZE - 1 : 0] crc_prev; |
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reg [24:0] POLY = 'h1B2B117; |
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reg [DATA_WIDTH-1:0]valid_data; |
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reg [7:0]valid_count = 0; |
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always_ff @( posedge clk_i ) |
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if( !rst_n ) |
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if( !rst_n )begin |
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crc_o <= INIT[CRC_SIZE - 1 : 0]; |
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valid_data <= 'b0; |
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end |
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else |
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begin |
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crc_o <= crc_prev; |
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end |
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// crc_o <= crc_prev; |
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for(valid_count = 0; valid_count < 140; valid_count = valid_count + 1) |
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if(valid_count <= a_in) |
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valid_data[valid_count] = data_i[valid_count];//;data_i[1*a_in +: 1]; |
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else |
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valid_data[valid_count] = 1'b0; |
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crc_o <= crc_prev; |
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end |
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generate |
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always_comb |
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begin |
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@@ -33,10 +50,12 @@ module crc_gen #( |
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crc_prev = crc; |
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for( int i = 0; i < DATA_WIDTH; i ++ ) |
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begin |
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crc_next[0] = crc_prev[CRC_SIZE - 1] ^ data_i[DATA_WIDTH - 1 - i]; |
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$display("Inside for Loop"); |
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crc_next[0] = crc_prev[CRC_SIZE - 1] ^ valid_data[DATA_WIDTH - 1 - i]; |
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$display("crc_next[%d] = %b",i,crc_next[i]); |
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for( int j = 1; j < CRC_SIZE; j++ ) |
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if( POLY[j] ) |
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crc_next[j] = crc_prev[j - 1] ^ crc_prev[CRC_SIZE - 1] ^ data_i[DATA_WIDTH - 1 - i]; |
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crc_next[j] = crc_prev[j - 1] ^ crc_prev[CRC_SIZE - 1] ^ valid_data[DATA_WIDTH - 1 - i]; |
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else |
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crc_next[j] = crc_prev[j - 1]; |
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crc_prev = crc_next; |
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