diff --git a/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv b/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv
index 7552760..ab4fab7 100644
--- a/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv
+++ b/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv
@@ -8,24 +8,41 @@ module crc_gen #(
           )(
             input                           clk_i,
             input                           rst_n,
-            input  [24:0]                   POLY,               
-            input  [DATA_WIDTH - 1 : 0]     data_i,           // Input Information bit 
-            output reg [CRC_SIZE - 1 : 0]   crc_o         // output CRC of information Input
+//            input  [24:0]                   POLY,
+            input  [7:0]                    a_in,               // Number of valid bits on input
+            input  [7:0]                    k_in,               // Number of valid bits on output  
+            input  [DATA_WIDTH - 1 : 0]     data_i,             // Input Information bit 
+            output reg [CRC_SIZE - 1 : 0]   crc_o               // output CRC of information Input
           );
           
           logic [CRC_SIZE - 1 : 0] crc = 0;
           logic [CRC_SIZE - 1 : 0] crc_next;
           logic [CRC_SIZE - 1 : 0] crc_prev;
+            
+          reg [24:0] POLY = 'h1B2B117;        
           
+          reg [DATA_WIDTH-1:0]valid_data;
+          
+          reg [7:0]valid_count = 0;
           
           always_ff @( posedge clk_i )
-            if( !rst_n )
+            if( !rst_n )begin
               crc_o <= INIT[CRC_SIZE - 1 : 0];
+              valid_data <= 'b0;
+             end
             else
             begin
-               crc_o <= crc_prev;
-            end  
+ //              crc_o <= crc_prev;
+     for(valid_count = 0; valid_count < 140; valid_count = valid_count + 1)
+     if(valid_count <= a_in)
+        valid_data[valid_count] = data_i[valid_count];//;data_i[1*a_in +: 1];
+     else
+        valid_data[valid_count] = 1'b0;  
+                crc_o <= crc_prev;
 
+            end  
+            
+            
           generate
            always_comb
              begin
@@ -33,10 +50,12 @@ module crc_gen #(
                crc_prev = crc;
                for( int i = 0; i < DATA_WIDTH; i ++ )
                  begin
-                   crc_next[0] = crc_prev[CRC_SIZE - 1] ^ data_i[DATA_WIDTH - 1 - i];
+                   $display("Inside for Loop");
+                   crc_next[0] = crc_prev[CRC_SIZE - 1] ^ valid_data[DATA_WIDTH - 1 - i];
+                   $display("crc_next[%d] = %b",i,crc_next[i]); 
                    for( int j = 1; j < CRC_SIZE; j++ )
                      if( POLY[j] )
-                       crc_next[j] = crc_prev[j - 1] ^ crc_prev[CRC_SIZE - 1] ^ data_i[DATA_WIDTH - 1 - i];
+                       crc_next[j] = crc_prev[j - 1] ^ crc_prev[CRC_SIZE - 1] ^ valid_data[DATA_WIDTH - 1 - i];
                      else
                        crc_next[j] = crc_prev[j - 1];
                    crc_prev = crc_next;