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- `timescale 1ns / 1ps
-
-
- module crc_gen #(
- parameter int CRC_SIZE = 24,
- parameter int DATA_WIDTH = 140,
- parameter bit [63 : 0] INIT = 'h0
- )(
- input clk_i,
- input rst_n,
- // input [24:0] POLY,
- input [7:0] a_in, // Number of valid bits on input
- input [7:0] k_in, // Number of valid bits on output
- input [DATA_WIDTH - 1 : 0] data_i, // Input Information bit
- output reg [CRC_SIZE - 1 : 0] crc_o // output CRC of information Input
- );
-
- logic [CRC_SIZE - 1 : 0] crc = 0;
- logic [CRC_SIZE - 1 : 0] crc_next;
- logic [CRC_SIZE - 1 : 0] crc_prev;
-
- reg [24:0] POLY = 'h1B2B117;
-
- reg [DATA_WIDTH-1:0]valid_data;
-
- reg [7:0]valid_count = 0;
-
- always_ff @( posedge clk_i )
- if( !rst_n )begin
- crc_o <= INIT[CRC_SIZE - 1 : 0];
- valid_data <= 'b0;
- end
- else
- begin
- // crc_o <= crc_prev;
- for(valid_count = 0; valid_count < 140; valid_count = valid_count + 1)
- if(valid_count <= a_in)
- valid_data[valid_count] = data_i[valid_count];//;data_i[1*a_in +: 1];
- else
- valid_data[valid_count] = 1'b0;
- crc_o <= crc_prev;
-
- end
-
-
- generate
- always_comb
- begin
- crc_next = crc;
- crc_prev = crc;
- for( int i = 0; i < DATA_WIDTH; i ++ )
- begin
- $display("Inside for Loop");
- crc_next[0] = crc_prev[CRC_SIZE - 1] ^ valid_data[DATA_WIDTH - 1 - i];
- $display("crc_next[%d] = %b",i,crc_next[i]);
- for( int j = 1; j < CRC_SIZE; j++ )
- if( POLY[j] )
- crc_next[j] = crc_prev[j - 1] ^ crc_prev[CRC_SIZE - 1] ^ valid_data[DATA_WIDTH - 1 - i];
- else
- crc_next[j] = crc_prev[j - 1];
- crc_prev = crc_next;
- end
- end
-
- endgenerate
- endmodule
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