AXI4_LiteMM/sources_1/imports/AXI4_liteMM/adderss_gen1.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 15.02.2021 20:04:18
// Design Name: 
// Module Name: adderss_gen1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module adderss_gen1(
        input core_clk,                 // input core clock.
        input rst_n,
        input en_cnt,                   // enable input to the counter.
        input [17:0]addr_in,            // base or start address from Axi_slave. 
        output reg [17:0]addrs_out,         // address to the memory map 
        output [1:0]count,
        output reg adr_rchd                  // 
            );
            
//wire core_clk;
reg  [1:0]cnt;// = 2'b11;
wire [17:0] addr_out;
//reg [17:0] addrs_out;
//reg adr_rchd;

always @ (posedge core_clk)
    begin
        if (!(rst_n && en_cnt))      // addded on 23022021.
                cnt <= 2'b00;
        else if (en_cnt)
                begin
                    cnt <= cnt + 1'b1;
                end
        else 
//            begin
//               if (cnt != 2'b00)        // addded on 22022021.
//                    cnt <= 2'b00;       // addded on 22022021.
//               else                     // addded on 22022021.
                    cnt <= cnt;   
            //end
          
    
    end
    assign addr_out = {15'b0,cnt};
    //assign adr_rchd = (addr_out == 18'd3) ? 1'b1 : 1'b0;
    assign count = cnt;
   // assign addrs_out = (en_cnt == 1'b1) ? (addr_in |addr_out ): 18'd0; 
always @ (posedge core_clk)
    if (en_cnt) 
        begin
            addrs_out <= (addr_in |addr_out );
            //adr_rchd <= (addr_out == 18'd3) ? 1'b1 : 1'b0;
          if(addr_out == 18'd3)
              adr_rchd <= 1'b1;
            else
              adr_rchd <= 1'b0;
        end
    else 
     addrs_out <= 18'dZ; 
endmodule