encoder_frozen_bit_insertion_rtl/sources_1/new/mux6to1.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 04.03.2021 10:10:40
// Design Name: 
// Module Name: mux6to1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mux6to1(indx_1,indx_2,indx_3,indx_4,indx_5,sel_indx,indx_out);
input [9:0]indx_1,indx_2,indx_3,indx_4,indx_5;
input [2:0]sel_indx;
output reg [9:0]indx_out;

always @(sel_indx or indx_1 or indx_2 or indx_3 or indx_4 or indx_5 )
    begin
        case (sel_indx)
            3'b000 :  indx_out = indx_1;
            3'b001 :  indx_out = indx_2;
            3'b010 :  indx_out = indx_3;
            3'b011 :  indx_out = indx_4;
            3'b100 :  indx_out = indx_5;
            //3'b101 :  indx_out = indx_6;
        default : indx_out = indx_1;
        endcase
    end
endmodule