`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 01.03.2021 16:56:29
// Design Name: 
// Module Name: lenght_match2out
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module lenght_match2out(K_bits,N_val,out_data);
input [511:0]K_bits;
input [9:0]N_val;
output reg [511:0]out_data;

always @ (*)
begin
    case (N_val)
        10'd32: out_data = {{479{1'b0}},K_bits[31:0]};
        10'd64: out_data = {{447{1'b0}},K_bits[63:0]};
        10'd128: out_data = {{383{1'b0}},K_bits[127:0]};
        10'd256: out_data = {{347{1'b0}},K_bits[163:0]};
        10'd512: out_data = {{347{1'b0}},K_bits[163:0]};
        
        default: out_data = {{479{1'b0}},K_bits[31:0]};
    endcase
end
endmodule

/* always @(Data_in_0 or sel_mx)
    begin
        case (sel_mx)
            4'b0000 :  Data_out = Data_in_0;
            4'b0001 :  Data_out = Data_in_1;
            4'b0010 :  Data_out = Data_in_2;
            4'b0011 :  Data_out = Data_in_3;
            4'b0100 :  Data_out = Data_in_4;
            4'b0101 :  Data_out = Data_in_5;
            4'b0110 :  Data_out = Data_in_6;
            4'b0111 :  Data_out = Data_in_7;
            4'b1000 :  Data_out = Data_in_8;
            4'b1001 :  Data_out = Data_in_9;
            4'b1010 :  Data_out = Data_in_10;
            4'b1011 :  Data_out = Data_in_11;
            4'b1100 :  Data_out = Data_in_12;
            4'b1101 :  Data_out = Data_in_13;
            4'b1110 :  Data_out = Data_in_14;
            4'b1111 :  Data_out = Data_in_15;
        endcase
    end*/