`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 04.03.2021 11:54:49
// Design Name: 
// Module Name: dwn_cntr
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module dwn_cntr(rst_n,clk, Enb,K_val,cnt_out, cnt_val_rst); 
input rst_n,Enb,clk; 
input [8:0]K_val;
output [9:0]cnt_out,cnt_val_rst;

reg [9:0]temp;


always @ (posedge clk)
begin
      if (!rst_n)  //(!rst_n) // commented on 04032021 for chceking.
        begin
         temp <= 0;
        end
      else if (temp == K_val)
         temp <= temp;  //10'd0; 
      else  if (Enb)
          temp <= temp + 1'b1;
      else
           temp <= temp;             
end
assign  cnt_out = K_val - temp;
assign  cnt_val_rst = temp;
endmodule