From 898fc76eeb64e0ba7ce58a49e2b01131d17f7cfd Mon Sep 17 00:00:00 2001 From: vikram Date: Fri, 5 Mar 2021 12:01:20 +0530 Subject: [PATCH] Encoder_frozen_bit_insertion_v2 --- .../encoder_frozen_bit_insertion_tb_1.sv | 63 +++++--- .../encoder_frozen_bit_insertion_rtl_1.sv | 137 ++++++++++++------ sources_1/new/dwn_cntr.v | 46 ++++++ sources_1/new/mux6to1.v | 40 +++++ 4 files changed, 223 insertions(+), 63 deletions(-) create mode 100644 sources_1/new/dwn_cntr.v create mode 100644 sources_1/new/mux6to1.v diff --git a/sim_1/imports/Downloads/encoder_frozen_bit_insertion_tb_1.sv b/sim_1/imports/Downloads/encoder_frozen_bit_insertion_tb_1.sv index a0eebfd..06e2d29 100644 --- a/sim_1/imports/Downloads/encoder_frozen_bit_insertion_tb_1.sv +++ b/sim_1/imports/Downloads/encoder_frozen_bit_insertion_tb_1.sv @@ -22,28 +22,30 @@ // encoder_frozen_bit_insertion_tb is written to verify encoder_frozen_bit_insertion_rtl module encoder_frozen_bit_insertion_tb(); -parameter N = 32; //12; // length of information+CRC+Frozen bits -parameter K = 16; //4; // length of information+CRC bits +//parameter N = 32; //12; // length of information+CRC+Frozen bits +//parameter K = 16; //4; // length of information+CRC bits reg clock_i = 1'b0; // system clock reg reset_ni = 1'b1; // active low synchronous reset reg [9:0]N_in; reg [8:0]K_in; -reg [K-1:0] msg_i; // input information+CRC bits +//reg [K-1:0] msg_i; // input information+CRC bits +reg [163:0] msg_i; // input information+CRC bits //wire [9:0] pc_pos1_o,pc_pos2_o,pc_pos3_o; // first, second, third positions to insert parity check bits -wire [N-1:0] msg_o; // information+CRC+frozen bits +//wire [N-1:0] msg_o; // information+CRC+frozen bits - wire [9:0] index_out32; - wire [9:0] index_out64; - wire [9:0] index_out128; - wire [9:0] index_out256; - wire [9:0] index_out512; + // wire [9:0] index_out32; + // wire [9:0] index_out64; + // wire [9:0] index_out128; + // wire [9:0] index_out256; + // wire [9:0] index_out512; wire [511:0]msg_1_out; // Instantiating and connecting the design module with test bench - encoder_frozen_bit_insertion_rtl #( - .N(N), - .K(K) - )DUT( + encoder_frozen_bit_insertion_rtl //#( + // .N(N), + // .K(K) + // ) + DUT( .clock_i(clock_i), .reset_ni(reset_ni), .msg_i(msg_i), @@ -52,12 +54,12 @@ wire [N-1:0] msg_o; // information+CRC+frozen bits //.pc_pos1_o(pc_pos1_o), //.pc_pos2_o(pc_pos2_o), //.pc_pos3_o(pc_pos3_o), - . msg_o(msg_o), +// . msg_o(msg_o), //. index_out32 ( index_out32), - . index_out64(index_out64), - . index_out128(index_out128), - . index_out256(index_out256), - . index_out512(index_out512), + // . index_out64(index_out64), + // . index_out128(index_out128), + //. index_out256(index_out256), + // . index_out512(index_out512), .msg_1_out(msg_1_out) ); @@ -72,13 +74,32 @@ wire [N-1:0] msg_o; // information+CRC+frozen bits K_in = 'd16; @(negedge clock_i); msg_i = 'hC8F5; //aaaabbbbccccddddaaaabbbbccccddddeeeeffff111122223333444455556666; // applying inputs to the DUT - #74 + #81 + + @(negedge clock_i); // waiting for the negedge of clock_i + reset_ni = 'd0; // activating the reset_ni @(negedge clock_i); - msg_i = 'hACF5; //'h3; + #4 reset_ni = 'd1; + + N_in = 'd64; + K_in = 'd20; + @(negedge clock_i); + msg_i = 'h0001; //'h3; //reset_ni = 'd0; + #140 + + @(negedge clock_i); // waiting for the negedge of clock_i + reset_ni = 'd0; // activating the reset_ni + @(negedge clock_i); + #4 reset_ni = 'd1; + + + @(negedge clock_i); + N_in = 'd128; + K_in = 'd12; @(negedge clock_i); msg_i = 'h9C83; //4'b1101; - #30 $finish; + #300 $finish; end endmodule diff --git a/sources_1/imports/Downloads/encoder_frozen_bit_insertion_rtl_1.sv b/sources_1/imports/Downloads/encoder_frozen_bit_insertion_rtl_1.sv index e3b37cc..559f628 100644 --- a/sources_1/imports/Downloads/encoder_frozen_bit_insertion_rtl_1.sv +++ b/sources_1/imports/Downloads/encoder_frozen_bit_insertion_rtl_1.sv @@ -20,43 +20,55 @@ ////////////////////////////////////////////////////////////////////////////////// // encoder_frozen_bit_insertion_rtl is written to insert frozen bits in between information bits, according to reliability sequence -module encoder_frozen_bit_insertion_rtl#( - parameter N = 32, //128, // length of information+CRC+Frozen bits - parameter K = 16 //64 // length of information+CRC bits -) ( +module encoder_frozen_bit_insertion_rtl +//#( + // parameter N = 32, //128, // length of information+CRC+Frozen bits + // parameter K = 16 //64 // length of information+CRC bits +//) +( input wire clock_i, // system clock input wire reset_ni, // active low synchronous reset + //input wire rst_in, // active low synchronous reset input wire [9:0]N_in, input wire [8:0]K_in, - input wire [K-1:0] msg_i, // input information+CRC bits + //input wire [K-1:0] msg_i, // input information+CRC bits + input wire [163:0] msg_i, //output reg [9:0] pc_pos1_o, // first position to insert parity check bit // output reg [9:0] pc_pos2_o, // second position to insert parity check bit //output reg [9:0] pc_pos3_o, // third position to insert parity check bit - output reg [N-1:0] msg_o, // information+CRC+frozen bits + //output reg [N-1:0] msg_o, // information+CRC+frozen bits // output reg [9:0]index_out32, - output reg [9:0]index_out64, - output reg [9:0]index_out128, - output reg [9:0]index_out256, - output reg [9:0]index_out512, + // output reg [9:0]index_out64, + // output reg [9:0]index_out128, + // output reg [9:0]index_out256, + // output reg [9:0]index_out512, output reg [511:0]msg_1_out ); - reg [9:0] pc_pos1_1, pc_pos2_1, pc_pos3_1; // internal registers to hold the parity check bit postions - reg [N-1:0] msg_1; // internal register to hold the output of frozen bit insertion + //reg [9:0] pc_pos1_1, pc_pos2_1, pc_pos3_1; // internal registers to hold the parity check bit postions + //reg [N-1:0] msg_1; // internal register to hold the output of frozen bit insertion - int i,j,k='d0,p='d0,q='d0,x='d0; // looping variables + // int i,j,k='d0,p='d0,q='d0,x='d0; // looping variables + +// reg [9:0]frz_pos[N-1:0]; // internal register to store reliability sequence depending on N value - reg [9:0]frz_pos[N-1:0]; // internal register to store reliability sequence depending on N value reg [4:0]rel_seq_enable; reg [9:0] addrs_cntr; //reg rel_seq_enable; reg rel_seq_en_dly,rel_seq_en_dly1; - wire [9:0]index_out32; - reg [9:0]index_out32_dly; - wire [8:0]indx_K; + wire [9:0]index_out32, index_out64,index_out128, index_out256,index_out512; + + reg [9:0]index_out32_dly,indexs_out; + reg [2:0]sel_indxs; + wire [9:0]indx_K; + + wire Dwn_en_r ,cnt_rst; + reg loc_rst; + reg loc_rst_dly; + wire [9:0]r_cnt_val_rst; // storing the frozen locations in rel_seq array (reliability in ascending order) /*reg [9:0]rel_seq[1023:0] = '{ 10'd0 , 10'd1 , 10'd2 , 10'd4 , 10'd8 , 10'd16 , 10'd32 , 10'd3 , 10'd5 , 10'd64 , 10'd9 , @@ -304,6 +316,7 @@ module encoder_frozen_bit_insertion_rtl#( {10'd31, 10'd30, 10'd29, 10'd27, 10'd23, 10'd15, 10'd28, 10'd22, 10'd25, 10'd26, 10'd21, 10'd14, 10'd13, 10'd19, 10'd11, 10'd7, 10'd24, 10'd20, 10'd12, 10'd18, 10'd10, 10'd17, 10'd6, 10'd9, 10'd5, 10'd3, 10'd16, 10'd8, 10'd4, 10'd2, 10'd1, 10'd0}; +/* // instantiatig a register(group of FF's) to hold the output and synchronize the module w.r.t clock and reset signals register #( .WIDTH('d10), // overriding the width of register with the length of output to be registered @@ -350,23 +363,26 @@ module encoder_frozen_bit_insertion_rtl#( .rstb(reset_ni), // connecting reset ports .din(msg_1), // connecting input of register with the value that needs to be registered .dout(msg_o) // connecting the registered output with the output port of current module - ); + ); */ ////// on 03032021.////////////// //// copy input msg to a reg. // decalare a output reg for all combinations -always @(N_in )//or K_in) //// enables of rel_seq are (rel_seq_512,rel_seq_256,rel_seq_128,rel_seq_64,rel_seq_32) +always @(N_in )//or K_in) //// enables of rel_seq are in the order of (rel_seq_512,rel_seq_256,rel_seq_128,rel_seq_64,rel_seq_32) begin case (N_in) - 10'd32 : begin rel_seq_enable = 5'b00001; end - 10'd64 : begin rel_seq_enable = 5'b00010; end - 10'd128 : begin rel_seq_enable = 5'b00100; end - 10'd256 : begin rel_seq_enable = 5'b01000; end - 10'd512 : begin rel_seq_enable = 5'b10000; end + 10'd32 : begin sel_indxs = 3'b000; rel_seq_enable = 5'b00001; end + 10'd64 : begin sel_indxs = 3'b001; rel_seq_enable = 5'b00010; end + 10'd128 : begin sel_indxs = 3'b010; rel_seq_enable = 5'b00100; end + 10'd256 : begin sel_indxs = 3'b011; rel_seq_enable = 5'b01000; end + 10'd512 : begin sel_indxs = 3'b100; rel_seq_enable = 5'b10000; end + default: begin sel_indxs = 3'b000; rel_seq_enable = 5'b00001; end endcase end -assign rel_seq_en = |rel_seq_enable; +assign rel_seq_en = |rel_seq_enable; // added a logic to rst for loading the values + +//assign reset_ni = rst_in || (~loc_rst_dly); always @ (posedge clock_i) begin if (!reset_ni) @@ -378,34 +394,58 @@ begin begin rel_seq_en_dly <= rel_seq_en; rel_seq_en_dly1 <= rel_seq_en_dly; - //rel_seq_en_dly1 <= indx_K ? rel_seq_en_dly: 1'b0; - index_out32_dly <= index_out32; + //index_out32_dly <= index_out32; /// comment on 04032021. + index_out32_dly <= indexs_out; + loc_rst_dly <= loc_rst; end end -//assign rel_seq_en_dly2 : indx_K ? rel_seq_en_dly: 1'b0; + + rel_seq_cntr addrss (.clk(clock_i),.rst_n(reset_ni),.En(rel_seq_en_dly),.N_val(N_in),.K_val(K_in),.adr_out(addrs_cntr)); ///// rel_seq mem's -relt_seq_32 rel_32 ( .en_32(rel_seq_enable[0]), .out_32(index_out32), .adr_32 (addrs_cntr)); -relt_seq_64 rel_64 ( .en_64(rel_seq_enable[1]), .out_64(index_out64), .adr_64 (addrs_cntr)); +relt_seq_32 rel_32 ( .en_32(rel_seq_enable[0]), .out_32(index_out32), .adr_32 (addrs_cntr)); +relt_seq_64 rel_64 ( .en_64(rel_seq_enable[1]), .out_64(index_out64), .adr_64 (addrs_cntr)); relt_seq_128 rel_128 ( .en_128(rel_seq_enable[2]), .out_128(index_out128), .adr_128 (addrs_cntr)); relt_seq_256 rel_256 ( .en_256(rel_seq_enable[3]), .out_256(index_out256), .adr_256 (addrs_cntr)); relt_seq_512 rel_512 ( .en_512(rel_seq_enable[4]), .out_512(index_out512), .adr_512 (addrs_cntr)); -counter_K counterK (.Clk(clock_i),.Load(rel_seq_en_dly1),.Kin(K_in),.Q(indx_K)); +//counter_K counterK (.Clk(clock_i),.Dwn_en(Dwn_en_r),.Load(rel_seq_en_dly1),.Kin(K_in),.Q(indx_K)); +//counter_K counterK (.Clk(clock_i),.Dwn_en(rel_seq_en_dly),.Load(rel_seq_en_dly1),.Kin(K_in),.Q(indx_K)); + +//assign Dwn_en_r = ~| indx_K; /// added for stopping the down counter. +//assign cnt_rst = ((~reset_ni) || Dwn_en_r); /// for restting the counter. + +always@(posedge clock_i) // operation done. +begin /// not used till 05-03-2021. + if (r_cnt_val_rst == K_in) + loc_rst = 1'b1; + else + loc_rst = 1'b0; +end + +dwn_cntr cntr_K (.rst_n(reset_ni),.clk(clock_i), .Enb(rel_seq_en_dly),.K_val(K_in),.cnt_out(indx_K),.cnt_val_rst(r_cnt_val_rst)); //working commented on 04032021. at 15:11pm. + +//dwn_cntr cntr_K (.rst_n(loc_rst),.clk(clock_i), .Enb(rel_seq_en_dly),.K_val(K_in),.cnt_out(indx_K),.cnt_val_rst(r_cnt_val_rst)); not working. + + +mux6to1 indexs (.indx_1(index_out32),.indx_2(index_out64),.indx_3(index_out128),.indx_4(index_out256),.indx_5(index_out512),.sel_indx(sel_indxs),.indx_out(indexs_out)); + always @ (negedge clock_i) begin if (rel_seq_en_dly1) -//msg_1_out[index_out32] = msg_i[K-1-x]; -//msg_1[frz_pos[q]] = msg_i[K-1-x]; - msg_1_out[index_out32_dly] = msg_i[indx_K]; + //msg_1[frz_pos[q]] = msg_i[K-1-x]; + msg_1_out[index_out32_dly] = msg_i[indx_K]; + //msg_1_out[indexs_out_dly] = msg_i[indx_K]; else msg_1_out = 511'd0; end +endmodule - + +//---------------------------------------- end ---------------------------------------// // always_comb begin /* begin : child_rel_seq //k = 'd0; @@ -441,9 +481,9 @@ end end*/ -endmodule +/* // register is written to synchronize a combiational logic w.r.t clock and reset signals module register #( parameter int WIDTH = 1, // width of the input and output of the register @@ -478,6 +518,7 @@ module register #( endgenerate endmodule +*/ /*always @ (posedge clk) begin @@ -492,15 +533,28 @@ begin end assign adr_out = tmp; endmodule */ - -module counter_K (Clk, Load,Kin, Q); -input Clk, Load; +////////////////////////// used in place of dwn_cntr /////////////////////////////////////////// +/*module counter_K (Clk,Dwn_en, Load,Kin, Q); +input Clk, Load,Dwn_en ; input [8:0]Kin; output [8:0] Q; reg [8:0] tmp; always @(posedge Clk) begin + if (Dwn_en) + begin + if (!Load || (tmp == 0)) // added by amit + tmp = Kin -1; + else + tmp = tmp - 1'b1; + end + else + tmp = tmp; + end + assign Q = Kin - tmp; +endmodule*/ + /* begin if (!Load || (tmp == 0)) // added by amit //if (!Load) // trueone. tmp = Kin -1; @@ -508,6 +562,5 @@ reg [8:0] tmp; tmp = tmp - 1'b1; // else // tmp = tmp; - end - assign Q = tmp; -endmodule + end */ + \ No newline at end of file diff --git a/sources_1/new/dwn_cntr.v b/sources_1/new/dwn_cntr.v new file mode 100644 index 0000000..fb69236 --- /dev/null +++ b/sources_1/new/dwn_cntr.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04.03.2021 11:54:49 +// Design Name: +// Module Name: dwn_cntr +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module dwn_cntr(rst_n,clk, Enb,K_val,cnt_out, cnt_val_rst); +input rst_n,Enb,clk; +input [8:0]K_val; +output [9:0]cnt_out,cnt_val_rst; + +reg [9:0]temp; + + +always @ (posedge clk) +begin + if (!rst_n) //(!rst_n) // commented on 04032021 for chceking. + begin + temp <= 0; + end + else if (temp == K_val) + temp <= temp; //10'd0; + else if (Enb) + temp <= temp + 1'b1; + else + temp <= temp; +end +assign cnt_out = K_val - temp; +assign cnt_val_rst = temp; +endmodule diff --git a/sources_1/new/mux6to1.v b/sources_1/new/mux6to1.v new file mode 100644 index 0000000..5254db9 --- /dev/null +++ b/sources_1/new/mux6to1.v @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04.03.2021 10:10:40 +// Design Name: +// Module Name: mux6to1 +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module mux6to1(indx_1,indx_2,indx_3,indx_4,indx_5,sel_indx,indx_out); +input [9:0]indx_1,indx_2,indx_3,indx_4,indx_5; +input [2:0]sel_indx; +output reg [9:0]indx_out; + +always @(sel_indx or indx_1 or indx_2 or indx_3 or indx_4 or indx_5 ) + begin + case (sel_indx) + 3'b000 : indx_out = indx_1; + 3'b001 : indx_out = indx_2; + 3'b010 : indx_out = indx_3; + 3'b011 : indx_out = indx_4; + 3'b100 : indx_out = indx_5; + //3'b101 : indx_out = indx_6; + default : indx_out = indx_1; + endcase + end +endmodule