shivakanta_project/axi_master_driver.sv

class axi_driver extends uvm_driver#(axi_seq_item);
`uvm_component_utils(axi_driver)

virtual intf vif;
axi_seq_item tx;
int temp[];
int burst_len;
int burst_size;
int total_tr;
int wrap_lower_boundary;
int wrap_upper_boundary;

function new(string name="axi_driver",uvm_component_parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
super.new();
tx=axi_seq_item::type_id::create("tx",this);

if(!uvm_config_db#(virtual intf)::get("this",*,"intf",vif)
`uvm_error(get_type_name(),$sformatf("failed for get vif"))
endfunction

task run_phase(uvm_phase phase)
forever begin
seq_item_port.get_next_item(tx);

drive();

seq_item_port.item_done(tx);
end
endtask

task drive();

if(tx.wr_rd)
begin

write_address();
write_data();
write_response();

end

else

read_address();

endtask
////////write address///////
task write_adress();
@(posedge vif.clk)

tx.awvalid<=1;
vif.awvalid<=tx.awvalid;


vif.awid<=tx.awid;
//vif.awaddr<=tx.awaddr;
vif.awsize<=tx.awsize;
vif.awlen<=tx.awlen;
vif.awburst<=tx.awburst;
//////////fixed burst////////////

if(tx.awburst==2'b00)

vif.awaddr<=tx.awaddr;

////////increament burst////////
else if(awburst==2'b01)begin

vif.awaddr<=tx.awaddr;
for(i=0;i<awlen;i++)
vif.awaddr<=(tx.awaddr+(2**awsize));
end
////////wrap burst/////////
else if(tx.awburst=2'b10)begin
begin
if(((tx.awaddr)%2**awsize)==0)begin
burst_len=tx.awlen+1;
burst_size=2**(tx.awsize);
total_tr=burst_len*burst_size;
wrap_lower_boundary=int'((tx.awaddr)/(total_tr))*total_tr;
wrap_upper_boundary=wrap_lower_boundary+total_tr;
end




vif.awlock<=tx.awlock;

@(posedge vif.clk)
 wait(vif.awready)


@(posedge vif.clk)
tx.awvalid<=0;
vif.awvalid<=tx.awvalid;

endtask
//////write data///////////
task write_data();
@posedge vif.clk)
tx.wvalid<=1;
vif.wvalid<=tx.wvalid;
vif.wid<=tx.wid;

foreach(tx.wdata[i,j])
begin
temp[i][8*i+:8]<=tx.wdata[i][j];
end

for(i=0;i<awlen+1;i++);
begin
vif.wdata<=temp[i];
tx.wvalid<=1;
vif.wvalid<=tx.wvalid;

vif.wlast<=awlen==i?1:0;
end
wait(vif.wready);

//endtask
@posedge vif.clk)
tx.wvalid<=0;
vif.wvalid<=tx.wvalid;
endtask

//////////write response //////////

task write_response();

@posedge vif.clk)
vif.bid<=tx.bid;
vif.bresp<=tx.bresp;
tx.bvalid<=1;
vif.bvalid<=tx.bvalid;

@posedge vif.clk)
wait(vif.bready);


@posedge vif.clk)
tx.bvalid<=0;
vif.bvalid<=tx.bvalid;

endtask

/////////read address/////////

task read_adress();
@(posedge vif.clk)

tx.arvalid<=1;
vif.arvalid<=tx.arvalid;


vif.arid<=tx.arid;
//vif.araddr<=tx.araddr;
vif.arsize<=tx.arsize;
vif.arlen<=tx.arlen;
vif.arburst<=tx.arburst;
//////////fixed burst////////////

if(tx.arburst==2'b00)

vif.araddr<=tx.araddr;

vif.arid<=tx.arid;
////////increament burst////////

else if(arburst==2'b01)begin

vif.araddr<=tx.araddr;
for(i=0;i<arlen;i++)
begin
vif.arid<=tx.arid;

vif.araddr<=(tx.araddr+(2**arsize));
end
////////wrap burst/////////
else if(tx.arburst=2'b10)begin
begin
if(((tx.araddr)%2**arsize)==0)begin

vif.arid<=tx.arid;
burst_len=tx.arlen+1;
burst_size=2**(tx.arsize);
total_tr=burst_len*burst_size;
wrap_lower_boundary=int'((tx.araddr)/(total_tr))*total_tr;
wrap_upper_boundary=wrap_lower_boundary+total_tr;
end

vif.arlock<=tx.arlock;

@(posedge vif.clk)
 wait(vif.arready)


@(posedge vif.clk)
tx.arvalid<=0;

vif.arvalid<=tx.arvalid;

endtask


endclass