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shivakanta_kondapalli 4 月之前
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共有 2 個文件被更改,包括 85 次插入0 次删除
  1. +45
    -0
      axi_config_objs.svh
  2. +40
    -0
      axi_env.sv

+ 45
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axi_config_objs.svh 查看文件

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import uvm_pkg::*;
/* Configuration object to configure the environment of Test Bench.
Configurable fields:
1. intf: Virtual Interface for the agents
2. active: To set the agent as active or passive */
class env_config#(parameter A_WIDTH = 16, D_WIDTH = 16) extends uvm_object;
`uvm_object_utils(env_config)
// variables
virtual axi_intf#(.D_WIDTH(D_WIDTH), .A_WIDTH(A_WIDTH)) intf;
// Master and Slave are active or passive
uvm_active_passive_enum active = UVM_ACTIVE;
function new(string name = "env_config");
super.new(name);
endfunction //new()
endclass //env_config extends uvm_object
// Configuration object which configures the sequence item generation
class test_config extends uvm_object;
`uvm_object_utils(test_config)
// Vartiables
int no_write_cases = 2;
int no_read_cases = 2;
// Set whether to produce aligned address or unalinged address
// -1: produce both aligned and unaligned randomly
// 0: produce unaligned adresses for all bursts
// 1: produce alligned adress for all bursts
byte isAligned = -1;
// Set the specific burst type for a test
// -1: produce all the burst type randomly
// 0: produce fixed bursts
// 1: produce incr bursts
// 2: produce wrap bursts
byte burst_type = -1;
function new(string name = "test_config");
super.new(name);
endfunction //new()
endclass //test_config extends uvm_object

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axi_env.sv 查看文件

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class axi_env extends uvm_env;
`uvm_component_utils(axi_env)
// Components
axi_master master;
axi_slave slave;
axi_scoreboard scb;
env_config env_cfg;
//
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction //new()
// Function: build_phase
extern function void build_phase(uvm_phase phase);
// Function: connect_phase
extern function void connect_phase(uvm_phase phase);
endclass //axi_env extends uvm_env
function void axi_env::build_phase(uvm_phase phase);
/* note: Do not call super.build_phase() from any class that is extended from an UVM base class! */
/* For more information see UVM Cookbook v1800.2 p.503 */
//super.build_phase(phase);
master = axi_master::type_id::create("master", this);
slave = axi_slave::type_id::create("slave", this);
scb = axi_scoreboard::type_id::create("scb", this);
endfunction: build_phase
function void axi_env::connect_phase(uvm_phase phase);
super.connect_phase(phase);
master.ap.connect(scb.m_ap_imp);
slave.ap.connect(scb.s_ap_imp);
endfunction: connect_phase

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