|
123456789101112131415161718192021222324252627282930313233343536373839404142 |
- // `include "uvm_pkg.sv"
- import uvm_pkg::*;
- `include "uvm_macros.svh"
- `include "axi_config_objs.svh"
- `include "axi_interface.sv"
- `include "axi_transaction.sv"
- `include "axi_write_seq.sv"
- `include "axi_read_seq.sv"
- `include "axi_m_driver.sv"
- `include "axi_m_monitor.sv"
- `include "axi_master_agent.sv"
- `include "axi_s_driver.sv"
- `include "axi_s_monitor.sv"
- `include "axi_slave_agent.sv"
- `include "axi_scoreboard.sv"
- `include "axi_env.sv"
- `include "axi_test.sv"
- `include "uvm_pkg.sv"
-
- // parameter A_WIDTH = 8; // Address bus width
- // parameter D_WIDTH = 128; // Data bus width
-
- module top;
- bit clk, rstn;
-
- always #5 clk = ~clk;
-
- initial rstn = 1;
-
- axi_intf#(.A_WIDTH(A_WIDTH), .D_WIDTH(D_WIDTH)) intf(clk, rstn);
- env_config env_cfg;
-
- initial begin
- env_cfg = new();
- env_cfg.intf = intf;
- uvm_config_db#(env_config)::set(null, "uvm_test_top", "config", env_cfg);
- uvm_config_db#(env_config)::set(null, "uvm_test_top.env.master", "config", env_cfg);
- uvm_config_db#(env_config)::set(null, "uvm_test_top.env.slave", "config", env_cfg);
- run_test("axi_base_test");
- end
-
- endmodule
|