//=============================AXI TRANSACTION CLASSS ==========================================// class axi_seq_item extends uvm_sequence_item; //FACTORY REGISTRATION 'uvm_object_utils(axi_seq_item); //WRITE ADDRESS CHANNEL rand logic [31:0] AWADDR; rand logic [3:0] AWLEN; rand logic [2:0] AWSIZE; rand logic [1:0] AWBURST; bit AWVALID; bit AWREADY; bit [1:0] AWLOCK; rand logic [2:0] AWPROT; rand logic [3:0] AWCACHE; rand bit [3:0] AWID; //WRITE DATA CHANNEL rand bit [3:0] WID; bit [2:0] WSTRB; rand logic [7:0] WDATA; bit WVALID; bit WREADY; bit WLAST; //WRITE RESPONSE CHANNEL bit [1:0] BRESP; bit BVALID; bit BREADY; //READ ADDRESS CHANNEL rand bit [3:0] ARID; rand logic [31:0] ARADDR; rand logic [2:0] ARSIZE; rand logic [1:0] ARBURST; rand logic [3:0] ARLEN; rand logic [2:0] ARPROT; rand logic [3:0] ARCACHE; rand logic [1:0] AELOCK; bit ARVALID; bit ARREADY; //READ DATA CHANNEL bit [3:0] RID; logic [7:0] RDATA; bit [1:0] RRESP; bit RVALID; bit RREADY; bit [3:0] RSTRB; bit RLAST; //==============================================4kb boundary=====================================// constraint awaddr_4k{ AWADDR % 4096 + (AWLEN + (1 << AWSIZE) <= 4096;} constraint araddr_4k{ ARADDR % 4096 + (ARLEN + (1 << ARSIZE) <= 4096;} //==============================================id must be same for bot read/write operation =====================================// constraint ali_w_addr{ AWID==ARID;} constraint ali_r_addr{WID==RID;} //==============================================burst type always not reserved=====================================// constraint burst_type{ AWBURST!=2'b11; ARBURST!=2'b11;} constraint wr_data_size{if(AWBURST==2'b01) (WDATA inside{[1:((2**AWSIZE)*16)]});} constraint rd_data_size{if(ARBURST==2'b01) (RDATA inside{[1:((2**ARSIZE)*16)]});} constraint wrap_data{ if(AWBURST==2'b10) WDATA inside {((2**AWSIZE)*2),((2**AWSIZE)*4),((2**AWSIZE)*8),((2**AWSIZE)*16)};} endclass