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@@ -0,0 +1,75 @@ |
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class axi_seq_item extends uvm_sequence_item;
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//FACTORY REGISTRATION
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'uvm_object_utils(axi_seq_item);
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//WRITE ADDRESS CHANNEL
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rand logic [31:0] AWADDR;
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rand logic [3:0] AWLEN;
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rand logic [2:0] AWSIZE;
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rand logic [1:0] AWBURST;
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bit AWVALID;
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bit AWREADY;
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bit [1:0] AWLOCK;
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rand logic [2:0] AWPROT;
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rand logic [3:0] AWCACHE;
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rand bit [3:0] AWID;
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//WRITE DATA CHANNEL
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rand bit [3:0] WID;
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bit [2:0] WSTRB;
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rand logic [7:0] WDATA;
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bit WVALID;
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bit WREADY;
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bit WLAST;
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//WRITE RESPONSE CHANNEL
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bit [1:0] BRESP;
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bit BVALID;
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bit BREADY;
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//READ ADDRESS CHANNEL
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rand bit [3:0] ARID;
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rand logic [31:0] ARADDR;
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rand logic [2:0] ARSIZE;
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rand logic [1:0] ARBURST;
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rand logic [3:0] ARLEN;
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rand logic [2:0] ARPROT;
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rand logic [3:0] ARCACHE;
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rand logic [1:0] AELOCK;
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bit ARVALID;
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bit ARREADY;
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//READ DATA CHANNEL
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bit [3:0] RID;
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logic [7:0] RDATA;
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bit [1:0] RRESP;
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bit RVALID;
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bit RREADY;
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bit [3:0] RSTRB;
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bit RLAST;
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//==============================================4kb boundary=====================================//
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constraint awaddr_4k{ AWADDR % 4096 + (AWLEN + (1 << AWSIZE) <= 4096;}
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constraint araddr_4k{ ARADDR % 4096 + (ARLEN + (1 << ARSIZE) <= 4096;}
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//==============================================id must be same for bot read/write operation =====================================//
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constraint ali_w_addr{ AWID==ARID;}
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constraint ali_r_addr{WID==RID;}
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//==============================================burst type always not reserved=====================================//
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constraint burst_type{ AWBURST!=2'b11; ARBURST!=2'b11;}
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constraint wr_data_size{if(AWBURST==2'b01)
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(WDATA inside{[1:((2**AWSIZE)*16)]});}
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constraint rd_data_size{if(ARBURST==2'b01)
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(RDATA inside{[1:((2**ARSIZE)*16)]});}
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constraint wrap_data{ if(AWBURST==2'b10)
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WDATA inside {((2**AWSIZE)*2),((2**AWSIZE)*4),((2**AWSIZE)*8),((2**AWSIZE)*16)};}
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endclass |