class axi_drv extends uvm_driver#(seq_item);
	`uvm_component_utils(axi_drv)
	virtual intf vif;
	seq_item txn;
	bit[7:0] temp [][];
	
	function new(string name="axi_drv",uvm_component parent);
	       super.new(name,parent);
       endfunction

       function void build_phase(uvm_phase phase);
	 super.build_phase(phase);
	 txn=seq_item::type_id::create("txn",this);
       if(!uvm_config_db#(virtual intf)::get(this,"","vif",vif)
	  `uvm_error("build_phase",$sformatf("failed to get confg_db"))
      endfunction

      task run_phase();
      forever begin
      seq_item_port.get(txn);
      drive(txn);
      seq_item_port.item_done();
       end
      endtask

      task drive(seq_item txn);
      @(posedge vif.clk)
       vif.rst<=1;
      repeat(2)@(posedge vif.clk)
       vif.rst<=0;
      @(posedge vif.clk)
      if(txn.write)
      begin
	 vif.awddr<=txn.awaddr;
	 vif.awlen <= txn.awlen;
	 vif.awsize<=txn.awsize;
	 vif.awburst<=txn.awburst;
	 vif.awlock<=txn.awlock;
	 vif.awid<=txn.awid;
	 vif.awvalid<=1;
	 wait(vif.awready)
         @(posedge vif.clk)
	 vif.awvalid<=0;
        @(posedge vif.clk)
         for(int i=0;i<trans.awlength+1;i++)
	 begin
         for(int j=0;j<2**trans.awsize;j++)
	 begin
         temp[i][j*8+:8]<= trans.wdata[i][j];
	 if(i=trans.awlength-1)
		 trans.wlast<=1;
	 else
		 trans.wlast<=0;
         end 
         end
         vif.wdata<=temp;

      endtask

      endclass