|
@@ -0,0 +1,114 @@ |
|
|
|
|
|
`include "uvm_macros.svh" |
|
|
|
|
|
import uvm_pkg::*; |
|
|
|
|
|
|
|
|
|
|
|
class axi_seq_item extends uvm_sequence_item; |
|
|
|
|
|
|
|
|
|
|
|
//`uvm_object_utils(axi_seq_item) |
|
|
|
|
|
|
|
|
|
|
|
function new(string name="axi_seq_item"); |
|
|
|
|
|
super.new(name); |
|
|
|
|
|
endfunction |
|
|
|
|
|
|
|
|
|
|
|
//write address signals |
|
|
|
|
|
rand bit write; |
|
|
|
|
|
rand logic [31:0] awaddr; |
|
|
|
|
|
rand bit [3:0] awid; |
|
|
|
|
|
rand logic [3:0] awlen; |
|
|
|
|
|
rand logic [2:0] awsize; |
|
|
|
|
|
rand logic [1:0] awburst; |
|
|
|
|
|
rand logic [1:0] awlock; |
|
|
|
|
|
|
|
|
|
|
|
//write data signals |
|
|
|
|
|
rand bit [3:0] wid; |
|
|
|
|
|
rand logic [31:0] wdata[][]; |
|
|
|
|
|
logic [3:0] wstrb; |
|
|
|
|
|
logic wlast; |
|
|
|
|
|
|
|
|
|
|
|
//write response signals |
|
|
|
|
|
rand bit [3:0] Bid; |
|
|
|
|
|
logic [1:0] Bresp; |
|
|
|
|
|
|
|
|
|
|
|
//read address signals |
|
|
|
|
|
rand logic [31:0] araddr; |
|
|
|
|
|
rand bit [3:0] arid; |
|
|
|
|
|
rand logic [3:0] arlen; |
|
|
|
|
|
rand logic [2:0] arsize; |
|
|
|
|
|
rand logic [1:0] arburst; |
|
|
|
|
|
rand logic [1:0] arlock; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//read data signals |
|
|
|
|
|
rand bit [3:0] rid; |
|
|
|
|
|
rand logic [31:0] rdata[][]; |
|
|
|
|
|
logic [3:0] rresp; |
|
|
|
|
|
rand logic rlast; |
|
|
|
|
|
|
|
|
|
|
|
`uvm_object_utils_begin(axi_seq_item) |
|
|
|
|
|
`uvm_field_int(awid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awaddr,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awsize,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awlen,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awburst,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awlock,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awvalid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(awready,UVM_ALL_ON) |
|
|
|
|
|
|
|
|
|
|
|
`uvm_field_int(wid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(wdata,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(wlast,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(wstrb,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(wvalid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(wready,UVM_ALL_ON) |
|
|
|
|
|
|
|
|
|
|
|
`uvm_field_int(Bid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(Bresp,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(Bvalid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(Bready,UVM_ALL_ON) |
|
|
|
|
|
|
|
|
|
|
|
`uvm_field_int(arid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(araddr,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arsize,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arlen,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arsize,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arburst,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arlock,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arvalid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(arready,UVM_ALL_ON) |
|
|
|
|
|
|
|
|
|
|
|
`uvm_field_int(rid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(rdata,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(rlast,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(rresp,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(rvalid,UVM_ALL_ON) |
|
|
|
|
|
`uvm_field_int(rready,UVM_ALL_ON) |
|
|
|
|
|
`uvm_object_utils_end |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//constraints for axi |
|
|
|
|
|
|
|
|
|
|
|
//axi 4kb boundary |
|
|
|
|
|
constraint axi_4kb {awaddr%4096+(2**awsize*(awlen+1))<=4096;} |
|
|
|
|
|
|
|
|
|
|
|
//constarint for exclusive access |
|
|
|
|
|
constraint exclusive_access { |
|
|
|
|
|
if(awlock==2'b01) |
|
|
|
|
|
awlen inside{1,3,7,15};} |
|
|
|
|
|
|
|
|
|
|
|
// aligned addr |
|
|
|
|
|
constraint aligned_addr {awaddr%2**awsize==0;} |
|
|
|
|
|
|
|
|
|
|
|
//wrap addr |
|
|
|
|
|
constraint wrap_addr { |
|
|
|
|
|
if(awburst==2'b 10) |
|
|
|
|
|
awlen inside{1,3,7,15};} |
|
|
|
|
|
//id's should be same |
|
|
|
|
|
constraint wid_awid {awid==wid;} |
|
|
|
|
|
|
|
|
|
|
|
//id's should be same |
|
|
|
|
|
constraint rid_awid {arid==rid;} |
|
|
|
|
|
|
|
|
|
|
|
endclass |
|
|
|
|
|
|
|
|
|
|
|
|