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- Interface intf(input bit clock,bit reset);
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- /////////////////write_address channel///////////////////
- input rand bit [3:0] awid;
- input rand logic [31:0]awaddr;
- input rand logic [3:0] awlen;
- input rand logic [2:0] awsize;
- input rand logic [1:0] awburst;
- input logic awvalid;
- output logic awready;
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- ////////////write_data channel///////////////////////////
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- input rand bit[3:0] wid;
- input rand logic [31:0]wdata[];
- input logic [3:0]wstrb;
- input logic wlast;
- input logic wvalid;
- output logic wready;
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- //////////write_response channel////////////////////////
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- output bit [3:0]bid;
- output logic [1:0]bresp;
- output logic bvalid;
- input logic bready;
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- /////////////read_address//////////////////////////////
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- input randc bit [3:0] arid;
- input rand logic [31:0]araddr;
- input rand logic [3:0]arlen;
- input rand logic [2:0]arsize;
- input rand logic [1:0]arburst;
- input logic arvalid;
- output logic arready;
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- //////////////read_data/////////////////////////////
- input bit [3:0] rid;
- input logic [31:0]rdata[];
- output logic [1:0]rresp;
- output logic rlast;
- output logic rvalid;
- input logic rready;
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- ///Value of 2'b11 on AWBURST is not permitted when AWVALID is high///
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- property p;
- @(posedge clk) awvalid |-> !(awburst==2'b11);
- endproperty
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- assert property(p);
- $display("assertion pass")
- else
- $uvm_fatal("assertion fail")
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- ///When AWVALID is high,AWADDR cannot be unknown values////
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- property p1;
- @(posedge clk) awvalid |-> !($isunknown(awaddr)) ;
- endproperty
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- assert property(p1)
- $display("assertion pass")
- else
- $uvm_fatal("assertion fail")
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- ///WVALID can assert before AWVALID///
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- property p2;
- @(posedge clk) wvalid |=> awvalid;
- endproperty
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- assert property(p2)
- $display("assertion pass")
- else
- $uvm_fatal("assertion fail")
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- ///AWREADY should be asserted before or after AWVALID is asserted////
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- property p3;
- @(posedge clk) awready |=> awvalid;
- endproperty
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- assert property(p3)
- $display("assertion pass")
- else
- $uvm_fatal("assertion fail")
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