axi_seqitem

axi_seqitem.sv.bak

@@ -0,0 +1,76 @@
+class seq_item extends uvm_sequence_item;
+`uvm_object_utils (seq_item)
+
+/////////////////write_address channel///////////////////
+ rand bit [3:0] awid;
+ rand logic [31:0]awaddr;
+ rand logic [3:0] awlen;
+ rand logic [2:0] awsize;
+ rand logic [1:0] awburst;
+ rand logic [3:0] awcache;
+ rand logic [2:0] awprot;
+ rand logic [1:0] awlock;
+ logic awvalid;
+ logic awready;
+
+////////////write_data channel///////////////////////////
+
+rand bit[3:0] wid;
+rand logic [31:0]wdata[];
+logic [3:0]wstrb;
+logic wlast;
+logic wvalid;
+logic wready;
+
+//////////write_response channel////////////////////////
+
+bit [3:0]bid;
+logic [1:0]bresp;
+logic bvalid;
+logic bready;
+
+/////////////read_address//////////////////////////////
+
+ randc bit [3:0] arid;
+ rand logic [31:0]araddr;
+ rand logic [3:0]arlen;
+ rand logic [2:0]arsize;
+ rand logic [1:0]arburst;
+ rand logic [3:0]arcache;
+ rand logic [2:0]arprot;
+ rand logic [1:0]awlock;
+ logic arvalid;
+ logic arready;
+
+//////////////read_data/////////////////////////////
+ bit [3:0] rid;
+ logic [31:0]rdata[];
+ logic [1:0]rresp;
+ logic rlast;
+ logic rvalid;
+ logic rready;
+
+bit wr_rd;
+int lower_boundary;
+int upper_boundary;
+
+constraint burst{awburst !=2'b11;}
+constraint wrap{if(awburst==2'b10) awlen inside {1,3,7,15};}
+constraint id {arlen == awlen;arsize == awsize;awid == wid;awid == arid;}
+constraint aligned {(awaddr%(2**awsize)==0);}
+constraint awburst{awburst inside {0,1,2}; awburst dist {2'b00:/10 , 2'b01:/60 , 2'b10:/30};}
+constraint arburst{arburst inside {0,1,2}; arburst dist {2'b00:/10 , 2'b01:/60 , 2'b10:/30};}
+constraint 4kb{((awaddr%4096) >=(awaddr+(awlen*awsize)%4096;}
+
+
+function new(string name = "seq_item");
+super.new(name);
+endfunction
+endclass
+
+
+
+
+
+
+