| @@ -0,0 +1,103 @@ | |||||
| Interface intf(input bit clock,bit reset); | |||||
| /////////////////write_address channel/////////////////// | |||||
| input rand bit [3:0] awid; | |||||
| input rand logic [31:0]awaddr; | |||||
| input rand logic [3:0] awlen; | |||||
| input rand logic [2:0] awsize; | |||||
| input rand logic [1:0] awburst; | |||||
| input logic awvalid; | |||||
| output logic awready; | |||||
| ////////////write_data channel/////////////////////////// | |||||
| input rand bit[3:0] wid; | |||||
| input rand logic [31:0]wdata[]; | |||||
| input logic [3:0]wstrb; | |||||
| input logic wlast; | |||||
| input logic wvalid; | |||||
| output logic wready; | |||||
| //////////write_response channel//////////////////////// | |||||
| output bit [3:0]bid; | |||||
| output logic [1:0]bresp; | |||||
| output logic bvalid; | |||||
| input logic bready; | |||||
| /////////////read_address////////////////////////////// | |||||
| input randc bit [3:0] arid; | |||||
| input rand logic [31:0]araddr; | |||||
| input rand logic [3:0]arlen; | |||||
| input rand logic [2:0]arsize; | |||||
| input rand logic [1:0]arburst; | |||||
| input logic arvalid; | |||||
| output logic arready; | |||||
| //////////////read_data///////////////////////////// | |||||
| input bit [3:0] rid; | |||||
| input logic [31:0]rdata[]; | |||||
| output logic [1:0]rresp; | |||||
| output logic rlast; | |||||
| output logic rvalid; | |||||
| input logic rready; | |||||
| ///Value of 2'b11 on AWBURST is not permitted when AWVALID is high/// | |||||
| property p; | |||||
| @(posedge clk) awvalid |-> !(awburst==2'b11); | |||||
| endproperty | |||||
| assert property(p); | |||||
| $display("assertion pass") | |||||
| else | |||||
| $uvm_fatal("assertion fail") | |||||
| ///When AWVALID is high,AWADDR cannot be unknown values//// | |||||
| property p1; | |||||
| @(posedge clk) awvalid |-> !($isunknown(awaddr)) ; | |||||
| endproperty | |||||
| assert property(p1) | |||||
| $display("assertion pass") | |||||
| else | |||||
| $uvm_fatal("assertion fail") | |||||
| ///WVALID can assert before AWVALID/// | |||||
| property p2; | |||||
| @(posedge clk) wvalid |=> awvalid; | |||||
| endproperty | |||||
| assert property(p2) | |||||
| $display("assertion pass") | |||||
| else | |||||
| $uvm_fatal("assertion fail") | |||||
| ///AWREADY should be asserted before or after AWVALID is asserted//// | |||||
| property p3; | |||||
| @(posedge clk) awready |=> awvalid; | |||||
| endproperty | |||||
| assert property(p3) | |||||
| $display("assertion pass") | |||||
| else | |||||
| $uvm_fatal("assertion fail") | |||||