|
- interface axi_if(input bit aclk,arst);
- //write address channel
- logic[31:0]awaddr;
- bit[3:0]awid;
- logic[3:0]awlen;
- logic[2:0]awsize;
- logic[1:0]awburst;
- logic[3:0]awcache;
- logic[2:0]awprot;
- logic[1:0]awlock;
- logic awvalid;'
- logic awready;
- //write data channel
- bit[3:0]wid;
- logic[3:0]wstrb;
- logic[31:0]wdata[$];
- logic wlast;
- logic wvalid;
- logic wready;
- //write response channel
- bit[3:0]bid;
- logic[1:0]bresp;
- logic bvalid;
- logic bready;
- //read address channel
- logic[31:0]araddr;
- bit[3:0]arid;
- logic[3:0]arlen;
- logic[2:0]arsize;
- logic[1:0]arburst;
- logic[3:0]arcache;
- logic[2:0]arprot;
- logic[1:0]arlock;
- logic arvalid;
- logic arready;
- //read data channel
- bit[3:0]rid;
- logic[31:0]rdata[$];
- logic rlast;
- logic[1:0]rresp;
- logic rvalid;
- logic rready;
- clocking drv_cb @(posedge aclk);
- default input #1 output #0;
- output awid; //write address channel
- output awaddr;
- output awlen;
- output awsize;
- output awburst;
- output awprot;
- output awcache;
- output awlock;
- output awvalid;
- input awready;
- output wid; //write data channel
- output wdata;
- output wstrb;
- output wlast;
- output wvalid;
- input wready; //write response channel
- input bid;
- input bresp;
- input bvalid;
- output bready;
- output arid; //read address channel
- output araddr;
- output arlen;
- output arsize;
- output arburst;
- output arprot;
- output arcache;
- output arlock;
- output arvalid;
- input arready;
- input rid; //read response channel
- input rdata;
- input rresp;
- input rlast;
- input rvalid;
- output rready;
- endclocking
-
- clocking mon_cb @(posedge clk);
- default input #1 output #0;
- input awid; //write address channel
- input awaddr;
- input awlen;
- input awsize;
- input awburst;
- input awprot;
- input awcache;
- input awlock;
- input awvalid;
- input awready;
- input wid; //write data channel
- input wdata;
- input wstrb;
- input wlast;
- input wvalid;
- input wready; //write response channel
- input bid;
- input bresp;
- input bvalid;
- input bready;
- input arid; //read address channel
- input araddr;
- input arlen;
- input arsize;
- input arburst;
- input arprot;
- input arcache;
- input arlock;
- input arvalid;
- input arready;
- input rid; //read data channel
- input rdata;
- input rresp;
- input rlast;
- input rvalid;
- input rready;
- endclocking
-
- modport drv_mod(clocking drv_cb,arst);
- modport mon_mod(clocking mon_cb,arst);
- endinterface
-
-
-
|