From 7051a9dff01accd6eb78be32e9e5c5cf0ca9221e Mon Sep 17 00:00:00 2001
From: aswini <aswini.brahamanapalli@bitsilica.com>
Date: Thu, 9 May 2024 10:23:10 +0530
Subject: [PATCH] aswini

---
 seq_item.sv | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 seq_item.sv

diff --git a/seq_item.sv b/seq_item.sv
new file mode 100644
index 0000000..1141d9b
--- /dev/null
+++ b/seq_item.sv
@@ -0,0 +1,102 @@
+class wrap_txn extends uvm_sequence_item;
+    function new(string name ="wrap_txn");
+        super.new(name)
+    endfunction
+    rand bit wr_rd;
+//write address channel
+    rand logic[31:0]awaddr;
+    rand bit[3:0]awid;
+    rand logic[3:0]awlen;
+    rand logic[2:0]awsize;
+    rand logic[1:0]awburst;
+    rand logic[3:0]awcache;
+    rand logic[2:0]awprot;
+    rand logic[1:0]awlock;
+         logic awvalid;'
+         logic awready;
+     '
+//write data channel
+    rand bit[3:0]wid;
+     logic[3:0]wstrb;
+    rand logic[31:0]wdata[$];
+         logic wlast;
+         logic wvalid;
+         logic wready;
+//write response channel
+    rand bit[3:0]bid;
+         logic[1:0]bresp;
+         logic bvalid;
+         logic bready;
+//read address channel
+    rand logic[31:0]araddr;
+    rand bit[3:0]arid;
+    rand logic[3:0]arlen;
+    rand logic[2:0]arsize;
+    rand logic[1:0]arburst;
+    rand logic[3:0]arcache;
+    rand logic[2:0]arprot;
+    rand logic[1:0]arlock;
+    logic arvalid;
+    logic arready;     
+//read data channel
+    rand bit[3:0]rid;
+         logic[31:0]rdata[$];
+         logic rlast;
+         logic[1:0]rresp; 
+         logic rvalid;
+         logic rready;
+
+    constraint write_id {awid == wid; wid == bid;}
+    constraint read_id {arid == rid;}
+    constraint wr_data {wdata.size()==awlen+1;}     
+    constraint write_unalign {awaddr%(2**awsize)!=0;}
+    constraint wrap {awburst ==2'b10; arburst ==2'b10;} 
+    constraint read_unalign {araddr%(2**arsize)!=0;}
+    function void post_randomize();
+        if(wr_rd = 1)
+        begin
+        for(int i=1;i<=(2**awsize);i++)
+          wstrb[i] = 1;
+        end
+    endfunction 
+    `uvm_object_param_utils_begin(wrap_txn)
+        `uvm_field_int(wr_rd,UVM_ALL_ON)
+        `uvm_field_int(awaddr,UVM_ALL_ON)
+        `uvm_field_int(awid,UVM_ALL_ON)
+        `uvm_field_int(awlen,UVM_ALL_ON)
+        `uvm_field_int(awsize,UVM_ALL_ON)
+        `uvm_field_int(awburst,UVM_ALL_ON)
+        `uvm_field_int(awcache,UVM_ALL_ON)
+        `uvm_field_int(awprot,UVM_ALL_ON)
+        `uvm_field_int(awlock,UVM_ALL_ON)
+        `uvm_field_int(awvalid,UVM_ALL_ON)
+        `uvm_field_int(awready,UVM_ALL_ON)
+        `uvm_field_int(wid,UVM_ALL_ON)
+        `uvm_field_queue_int(wdata,UVM_ALL_ON)
+        `uvm_field_int(wstrb,UVM_ALL_ON)
+        `uvm_field_int(wlast,UVM_ALL_ON)
+        `uvm_field_int(wvalid,UVM_ALL_ON)
+        `uvm_field_int(wready,UVM_ALL_ON)
+        `uvm_field_int(bid,UVM_ALL_ON)
+        `uvm_field_int(bresp,UVM_ALL_ON)
+        `uvm_field_int(araddr,UVM_ALL_ON)
+        `uvm_field_int(arid,UVM_ALL_ON)
+        `uvm_field_int(arlen,UVM_ALL_ON)
+        `uvm_field_int(arsize,UVM_ALL_ON)
+        `uvm_field_int(arburst,UVM_ALL_ON)
+        `uvm_field_int(arcache,UVM_ALL_ON)
+        `uvm_field_int(arprot,UVM_ALL_ON)
+        `uvm_field_int(arlock,UVM_ALL_ON)
+        `uvm_field_int(arvalid,UVM_ALL_ON)
+        `uvm_field_int(arready,UVM_ALL_ON)
+        `uvm_field_int(rid,UVM_ALL_ON)
+        `uvm_field_queue_int(rdata,UVM_ALL_ON)
+        `uvm_field_int(rlast,UVM_ALL_ON)
+        `uvm_field_int(rresp,UVM_ALL_ON)
+        `uvm_field_int(rvalid,UVM_ALL_ON)
+        `uvm_field_int(rready,UVM_ALL_ON)
+    `uvm_object_utils_end
+endclass
+    
+    
+