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  1. /*`timescale 1ns / 1ns

  2. //////////////////////////////////////////////////////////////////////////////////

  3. // Company: 

  4. // Engineer: 

  5. // 

  6. // Create Date: 02/24/2021 08:03:07 PM

  7. // Design Name: 

  8. // Module Name: sc_decoder_fsm

  9. // Project Name: 

  10. // Target Devices: 

  11. // Tool Versions: 

  12. // Description: 

  13. // 

  14. // Dependencies: 

  15. // 

  16. // Revision:

  17. // Revision 0.01 - File Created

  18. // Additional Comments:

  19. // 

  20. //////////////////////////////////////////////////////////////////////////////////

  21. `define BITS 8

  22. module sc_decoder_fsm #(parameter BITS=8, N=11'd16)(

  23. input clk, rst,

  24. input in_valid,

  25. input signed [N-1:0][BITS-1:0]y,

  26. input [N-1:0]f, 

  27. output logic [N-1:0]u_cap,

  28. output logic [N-1:0]v_final,

  29. output logic out_valid

  30. );

  31. 

  32. 

  33. // Function to calculate f(r1,r2) = sgn(r1) * sgn(r2) * min(|r1|,|r2|)

  34. function void fminsum_calc;

  35.         input  signed [`BITS-1:0] a;

  36.         input  signed [`BITS-1:0] b;

  37.         output signed [`BITS-1:0] c;

  38.         

  39.         logic [`BITS-2:0] abs_a;

  40.         logic [`BITS-2:0] abs_b;

  41.         logic [`BITS-2:0] abs_c;

  42.         

  43.         // Mod value of a and b  

  44.         abs_a = (a[`BITS-1]) ? ~a[`BITS-2:0] + 1'b1 : a[`BITS-2:0];

  45.         abs_b = (b[`BITS-1]) ? ~b[`BITS-2:0] + 1'b1 : b[`BITS-2:0];

  46.         

  47.         // Multiplication of sign i.e. XOR

  48.         c[`BITS-1] = a[`BITS-1] ^ b[`BITS-1];

  49.         

  50.         // Minimum value between a and b

  51.         abs_c = (abs_b < abs_a) ? abs_b : abs_a;

  52.         

  53.         // Final Minsum of a and b

  54.         c[`BITS-2:0] = (c[`BITS-1]) ? ~abs_c + 1'b1 : abs_c;

  55.         

  56. endfunction

  57.     

  58. 

  59. // Function to Calculate g(r1,r2,u) = r2 + ((1-2u) * r1)

  60. function  void g_calc;

  61.         input signed [`BITS-1:0] a;

  62.         input signed [`BITS-1:0] b;

  63.         input u;

  64.         output signed [`BITS:0] c;

  65.         

  66.        // when u == 0 => c = b - a 

  67.        // When u == 1 => c = b + a  

  68.         c = u  ? (b + (~a+1)) : (b + a) ;

  69. endfunction

  70. 

  71. 

  72. //parameters and signals declarations

  73. localparam d=$clog2(N);  //N=4, d=2(0 & 1)

  74. logic [N-1:0]u;

  75. logic [d:0]temp_index_f,temp_index_g;

  76. reg signed [BITS-1:0] LRU[2];

  77. reg [N-1:0]v;

  78. logic [N-1:0][BITS-1:0]L_in, L_out;

  79. logic [N-1:0]v_in, v_out;

  80. logic ena_v,enb_v,wea_v;

  81. logic ena_L,enb_L,wea_L;

  82. logic [1:0]counter,counter_reg;

  83. logic [11:0]jL1,jL2,jR1,jR2,jR3,jU1,jU2;

  84. logic [4:0] c_state, n_state;

  85. 

  86. 

  87. wire [N-1:0]u_cap_1;  

  88. wire [N-1:0]v_final_1;

  89. //wire out_valid_1;

  90. 

  91.       

  92. //Auxiliary registers declarations

  93. logic [d:0] depth,depth_reg;

  94. logic [d:0] node,node_reg;

  95. logic [11:0]tmp_L,tmp_L_reg, tmp_R,tmp_R_reg,tmp_U, tmp_U_reg;

  96. 

  97. //FSM States

  98. localparam idle=5'd0, root=5'd1, wait_L_logic=5'd2, wait_L=5'd3, state_L=5'd4, wait_R_logic=5'd5, wait_R=5'd6, state_R=5'd7;

  99. localparam wait_U_logic=5'd8, wait_U=5'd9, state_U=5'd10,wait_LRU_logic=5'd11, wait_LRU=5'd12, state_LRU=5'd13;

  100. localparam wait_lnode_logic=5'd14, wait_lnode=5'd15, state_lnode=5'd16,wait_lstate_logic=5'd17, wait_lstate=5'd18, state_last=5'd19;

  101. 

  102. //BlockRAM Instantiations

  103.  bram_v #(.ADDR_WIDTH(d-1),.DATA_WIDTH(N),.DEPTH(2**(d-1))) bram_v_i (

  104. .clk(clk),.ena(ena_v),.enb(enb_v),

  105. .addra(depth_reg-1'b1),

  106. .addrb(depth_reg),

  107. .wea(wea_v),

  108. .dia(v_in),

  109. .dob(v_out)

  110. );

  111. 

  112. bram_L #(.ADDR_WIDTH(d-1),.DATA_WIDTH(N*BITS),.DEPTH(2**(d-1)),.N(N)) bram_L_i (

  113. .clk(clk),.ena(ena_L),.enb(enb_L),

  114. .addra(depth_reg),

  115. .addrb(depth_reg-1'b1),

  116. .wea(wea_L),

  117. .dia(L_in),

  118. .dob(L_out)

  119. );

  120. 

  121. //output assignment

  122. for(genvar i=0; i<N; i++)

  123.  begin

  124.  assign u_cap_1[i] = u[i];

  125.  end

  126.  assign v_final_1 = v;

  127.  

  128. //  assign out_valid_1 = (n_state == state_lnode) ? 1'b1 : 1'b0;

  129.  assign out_valid=(n_state==state_last)?1'b1:1'b0;

  130. 

  131. 

  132. // Sequential Logic - FSM State and Data Registers

  133. always_ff@(posedge clk) 

  134. begin

  135.     if(rst==1) 

  136.     begin

  137.         u_cap     <= 'b0;

  138.         v_final   <= 'b0;

  139.  

  140.         c_state <= idle;

  141.         depth_reg<=0;

  142.         node_reg<=0;

  143.         counter_reg<=0;

  144.         tmp_L_reg<=0;

  145.         tmp_R_reg<=0;

  146.         tmp_U_reg<=0;

  147.      end

  148.     else 

  149.     begin

  150. //        out_valid <= out_valid_1;          

  151. //        v_final   <= v_final_1;

  152.         if(out_valid)

  153.            begin

  154.              u_cap     <= u;

  155.           end

  156.         else

  157.           begin

  158.              u_cap     <= u_cap;

  159.           end

  160.         c_state <= n_state;

  161.         depth_reg<=depth;

  162.         node_reg<=node;

  163.         counter_reg<=counter;

  164.         tmp_L_reg<=tmp_L;

  165.         tmp_R_reg<=tmp_R;

  166.         tmp_U_reg<=tmp_U;

  167.     end

  168. end

  169. 

  170. //Combinational Logic - FSM Next State Logic

  171. always_comb 

  172. begin  

  173. //                  depth=0; node=0;  

  174.  //                   ena_L=0;wea_L=0;enb_L=0;

  175.                     tmp_L=0; tmp_R=0; tmp_U=0;

  176.                    counter=0; ena_v=0;wea_v=0; enb_v=0; n_state = 0;

  177.   if(in_valid==1)

  178.     case(c_state)

  179.     idle:       begin 

  180.                    depth=0; node=0; counter=0; tmp_L=0; tmp_R=0; tmp_U=0;

  181.                    ena_L=0;wea_L=0;enb_L=0;

  182.                    ena_v=0;wea_v=0; enb_v=0;

  183.                     if(out_valid==1)

  184.                         n_state=idle;

  185.                     else

  186.                         n_state=root;    

  187.                 end

  188.           

  189.     root:       begin

  190.                   depth=depth_reg;node=node_reg;

  191.                   ena_L=1;wea_L=1;enb_L=0;

  192.                   ena_v=0;wea_v=0; enb_v=0;     

  193.                   for(int k=0; k<N; k++)

  194.                   L_in[k]=y[k];

  195.                   n_state=wait_L_logic;

  196.                 end

  197.    wait_L_logic: 

  198.                 begin

  199.                  depth=depth_reg+1; node=((2*node_reg)+1); tmp_L=0;

  200.                  ena_L=0;wea_L=0;enb_L=1;

  201.                  ena_v=0;wea_v=0; enb_v=0; 

  202.                  n_state=wait_L;

  203.                 end

  204.     wait_L:    begin

  205.                   n_state=state_L; 

  206.                end

  207.     state_L:    begin     

  208.                     ena_L=1;wea_L=1;enb_L=0;

  209.                     ena_v=0;wea_v=0; enb_v=0;

  210.                     tmp_L=tmp_L_reg+1;

  211.                     temp_index_f=((N/(2**(depth+1)))*((2*(node)+1)-((2**(depth+1))-1))); 

  212. //                    temp_index_f=((N>>(2**(depth+1)))*((2*(node)+1)-((2**(depth+1))-1))); 

  213.                     jL1=(tmp_L_reg)+temp_index_f;

  214.                     jL2=(tmp_L_reg)+temp_index_f+(N/(2**depth));

  215. //                    jL2=(tmp_L_reg)+temp_index_f+(N>>(2**depth));

  216.                     fminsum_calc(L_out[jL1],L_out[jL2],L_in[jL1]); 

  217.                                                                

  218.                     if(tmp_L< (N/(2**depth)))    

  219. //                    if(tmp_L< (N>>(2**depth)))    

  220.                         n_state=state_L;                 

  221.                     else if(depth<d)

  222.                         n_state=wait_L_logic;

  223.                     else

  224.                         n_state=wait_LRU_logic;

  225.                 end

  226. 

  227.      wait_R_logic: begin

  228.                     depth=depth_reg-1; node=node_reg+1; tmp_R=0;

  229.                     n_state=wait_R;

  230.                    end                       

  231.      wait_R:      begin

  232.                     ena_L=0;wea_L=0;enb_L=1;

  233.                     ena_v=0;wea_v=0; enb_v=1; 

  234.                     n_state=state_R; 

  235.                  end                       

  236.     

  237.     state_R:    begin 

  238.                    ena_L=1;wea_L=1;enb_L=0;

  239.                    ena_v=0;wea_v=0; enb_v=0;

  240.                    tmp_R=tmp_R_reg+1;

  241.                    temp_index_f=((N/(2**(depth+1)))*((2*(node)+1)-((2**(depth+1))-1)));

  242.                    temp_index_g=((N/(2**(depth+1)))*((2*(node-1)+1)-((2**(depth+1))-1)));

  243.                    jR1=(tmp_R_reg)+temp_index_g;

  244.                    jR2=(tmp_R_reg)+temp_index_g+(N/(2**depth));

  245.                    jR3=(tmp_R_reg)+temp_index_f;

  246.                    g_calc(L_out[jR1],L_out[jR2],v_out[jR1],L_in[jR3]);

  247.                       

  248.                    if(tmp_R< (N/(2**depth)))    

  249.                        n_state=state_R;

  250.                    else if(node==((2**d)-2)) 

  251.                        n_state=wait_lnode_logic;

  252.                    else if(depth==d)

  253.                        n_state=wait_LRU_logic;

  254.                    else 

  255.                        n_state = wait_L_logic;                                               

  256.                end                   

  257.                             

  258.      wait_U_logic: begin

  259.                      depth=depth_reg-1; node=(node_reg-2)/2; tmp_U=0;

  260.                      n_state=wait_U;

  261.                    end                       

  262.      wait_U:     begin

  263.                      ena_L=0;wea_L=0;enb_L=0;

  264.                      ena_v=0;wea_v=0; enb_v=1; 

  265.                      n_state=state_U; 

  266.                  end                        

  267.     state_U:    begin

  268.                      ena_L=0;wea_L=0;enb_L=0;

  269.                      ena_v=1;wea_v=1; enb_v=0;

  270.                      tmp_U=tmp_U_reg+1;

  271.                      temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1))); 

  272.                      jU1=(tmp_U_reg)+temp_index_f;

  273.                      jU2=(tmp_U_reg)+temp_index_f+(N/(2**(depth)));

  274.                      v_in[jU1] = v_out[jU1] ^ v_out[jU2]; 

  275.                      v_in[jU2] = v_out[jU2]; 

  276.                                     

  277.                      if(tmp_U<(N/(2**(depth)))) 

  278.                          n_state=state_U;

  279. //                     else if(depth>0 && node%2==0)  

  280.                      else if(depth>0 && node[0]==0)  

  281.                          n_state = wait_U_logic;                          

  282.                      else if(depth>0 && node!=0)

  283.                          n_state=wait_R_logic;

  284.                      else              

  285.                          n_state=wait_lstate_logic;         

  286.                   end 

  287.     wait_LRU_logic: begin

  288.                      depth=depth_reg; node=(node_reg-1)/2;

  289. //                     depth=depth_reg; node=(node_reg-1)>>1;

  290.                       n_state=wait_LRU;

  291.                     end                         

  292.     wait_LRU:   begin

  293.                     ena_L=0;wea_L=0;enb_L=1;

  294.                     ena_v=0;wea_v=0; enb_v=0; 

  295.                     n_state=state_LRU; 

  296.                 end                                                            

  297.  

  298.     state_LRU:  begin

  299.                     ena_L=0;wea_L=0;enb_L=0;

  300.                     ena_v=1;wea_v=1; enb_v=0;

  301.                     temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1)));

  302. //                    temp_index_f=((N>>(2**(depth)))*((2*node+1)-((2**(depth))-1)));

  303.                     fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);

  304. //                    u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0);

  305.                     u[(2*node)+2-N]=(f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1 : 0);

  306.                     g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);

  307. //                    u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0);

  308.                     u[(2*node)+3-N]=(f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1 : 0);

  309.                     v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N];

  310.                     v_in[temp_index_f+1]=u[(2*node)+3-N];                                                       

  311.                     

  312. //                    if(node%2==1)

  313.                     if(node[0])               

  314.                         n_state = wait_R_logic;                                 

  315.                     else                          

  316.                         n_state=wait_U_logic;

  317.                     end  

  318.     wait_lnode_logic:  begin

  319.                          depth=depth_reg+1; node=node_reg;

  320.                          n_state=wait_lnode;

  321.                        end                         

  322.     wait_lnode:        begin

  323.                          ena_L=0;wea_L=0;enb_L=1;

  324.                          ena_v=0;wea_v=0; enb_v=0; 

  325.                          n_state=state_lnode; 

  326.                        end 

  327.      state_lnode:      begin  

  328.                          ena_L=0;wea_L=0;enb_L=0;

  329.                          ena_v=1;wea_v=1; enb_v=0;

  330.                          temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1)));

  331.  //                        temp_index_f=((N>>(2**(depth)))*((2*node+1)-((2**(depth))-1)));

  332.                          fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);

  333. //                         u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0);

  334.                          u[(2*node)+2-N]=(f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1 : 0);

  335.                          g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);

  336. //                         u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0);   

  337.                          u[(2*node)+3-N]=(f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1 : 0);   

  338.                          v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N];

  339.                          v_in[temp_index_f+1]=u[(2*node)+3-N];                                                    

  340.                          n_state = wait_U_logic; 

  341.                        end 

  342.      wait_lstate_logic: begin

  343.                          depth=depth_reg;  node=node_reg;

  344.                          n_state=wait_lstate;

  345.                         end                         

  346.      wait_lstate:       begin

  347.                           ena_L=0;wea_L=0;enb_L=1;

  348.                           ena_v=0;wea_v=0; enb_v=0; 

  349.                           n_state=state_last; 

  350.                         end

  351.      state_last:       begin

  352.                           ena_L=0;wea_L=0;enb_L=0;

  353.                           ena_v=1;wea_v=1; enb_v=0;

  354.                           v=v_out;

  355.                           n_state=idle;

  356.                         end                                            

  357.     endcase  

  358. else    n_state = idle;                    

  359. end

  360. endmodule

  361. */

  362. 

  363. 

  364. `timescale 1ns / 1ns

  365. //////////////////////////////////////////////////////////////////////////////////

  366. // Company: 

  367. // Engineer: 

  368. // 

  369. // Create Date: 02/24/2021 08:03:07 PM

  370. // Design Name: 

  371. // Module Name: sc_decoder_fsm

  372. // Project Name: 

  373. // Target Devices: 

  374. // Tool Versions: 

  375. // Description: 

  376. // 

  377. // Dependencies: 

  378. // 

  379. // Revision:

  380. // Revision 0.01 - File Created

  381. // Additional Comments:

  382. // 

  383. //////////////////////////////////////////////////////////////////////////////////

  384. `define BITS 8

  385. module sc_decoder_fsm #(parameter BITS=8, N=11'd128)(

  386. input clk, rst,

  387. input in_valid,

  388. input signed [N-1:0][BITS-1:0] y,

  389. input [N-1:0]f, 

  390. output wire [N-1:0]u_cap,

  391. output wire [N-1:0]v_final,

  392. output wire out_valid

  393. );

  394. 

  395. 

  396. //function for fminsum calculation

  397. function void fminsum_calc;

  398.         input signed [`BITS-1:0] a;

  399.         input signed [`BITS-1:0] b;

  400.        output signed [`BITS-1:0] c;

  401.         

  402.         logic [`BITS-2:0] abs_a;

  403.         logic [`BITS-2:0] abs_b;

  404.         logic [`BITS-2:0] abs_c;

  405. 

  406.         abs_a = (a[`BITS-1]) ? ~a[`BITS-2:0] + 1'b1 : a[`BITS-2:0];

  407.         abs_b = (b[`BITS-1]) ? ~b[`BITS-2:0] + 1'b1 : b[`BITS-2:0];

  408.         c[`BITS-1] = a[`BITS-1] ^ b[`BITS-1];

  409.         abs_c = (abs_b < abs_a) ? abs_b : abs_a;

  410.         c[`BITS-2:0] = (c[`BITS-1]) ? ~abs_c + 1'b1 : abs_c;

  411.         

  412.     endfunction

  413.     

  414. //function for g-value calculation

  415.     function  void g_calc;

  416.         input signed [`BITS-1:0] a;         

  417.         input signed [`BITS-1:0] b;

  418.         input u;

  419.         output signed [`BITS:0] c;

  420.         c = (u == 0) ? (b + a) : (b + (~a+1'b1));

  421.     endfunction

  422. 

  423. //parameters and signals declarations

  424. localparam d=$clog2(N);  //N=4, d=2(0 & 1)

  425. //localparam n=2*N-1; //(2**d)-1;

  426. //localparam cmax=0;

  427. logic u[N];

  428. logic [d:0]temp_index_f,temp_index_g;

  429. reg signed [BITS-1:0] LRU[2];

  430. reg [N-1:0]v;

  431. logic [N-1:0][BITS-1:0]L_in, L_out;

  432. logic [N-1:0]v_in, v_out;

  433. logic ena_v,enb_v,wea_v;

  434. logic ena_L,enb_L,wea_L;

  435. //logic [1:0]counter,counter_reg;

  436. logic [11:0]jL1,jL2,jR1,jR2,jR3,jU1,jU2;

  437. logic [4:0] c_state, n_state;

  438. 

  439. //Auxiliary registers declarations

  440. logic [d:0] depth,depth_reg;

  441. logic [d:0] node,node_reg;

  442. logic [11:0]tmp_L,tmp_L_reg, tmp_R,tmp_R_reg,tmp_U, tmp_U_reg;

  443. 

  444. //FSM States

  445. localparam idle=5'd0, root=5'd1, wait_L_logic=5'd2, wait_L=5'd3, state_L=5'd4, wait_R_logic=5'd5, wait_R=5'd6, state_R=5'd7;

  446. localparam wait_U_logic=5'd8, wait_U=5'd9, state_U=5'd10,wait_LRU_logic=5'd11, wait_LRU=5'd12, state_LRU=5'd13;

  447. localparam wait_lnode_logic=5'd14, wait_lnode=5'd15, state_lnode=5'd16,wait_lstate_logic=5'd17, wait_lstate=5'd18, state_last=5'd19;

  448. 

  449. //BlockRAM Instantiations

  450.  bram_v #(.ADDR_WIDTH(d-1),.DATA_WIDTH(N),.DEPTH(2**(d-1))) bram_v_i (

  451. .clk(clk),.ena(ena_v),.enb(enb_v),

  452. .addra(depth_reg-1),

  453. .addrb(depth_reg),

  454. .wea(wea_v),

  455. .dia(v_in),

  456. .dob(v_out)

  457. );

  458. 

  459. bram_L #(.ADDR_WIDTH(d-1),.DATA_WIDTH(N*BITS),.DEPTH(2**(d-1)),.N(N)) bram_L_i (

  460. .clk(clk),.ena(ena_L),.enb(enb_L),

  461. .addra(depth_reg),

  462. .addrb(depth_reg-1),

  463. .wea(wea_L),

  464. .dia(L_in),

  465. .dob(L_out)

  466. );

  467. 

  468. //output assignment

  469. for(genvar i=0; i<N; i++)

  470.  begin

  471.  assign u_cap[i] = u[i];

  472.  end

  473.  assign v_final=v;

  474.  assign out_valid=(n_state==state_lnode)?1'b1:1'b0;

  475. // assign out_valid=(n_state==state_last)?1'b1:1'b0;

  476.  

  477. 

  478. // Sequential Logic - FSM State and Data Registers

  479. always_ff@(posedge clk) 

  480. begin

  481.     if(rst==1) 

  482.     begin

  483.         c_state <= idle;

  484.         depth_reg<=0;

  485.         node_reg<=0;

  486. //        counter_reg<=0;

  487.         tmp_L_reg<=0;

  488.         tmp_R_reg<=0;

  489.         tmp_U_reg<=0;

  490.      end

  491.     else 

  492.     begin

  493.         c_state <= n_state;

  494.         depth_reg<=depth;

  495.         node_reg<=node;

  496. //        counter_reg<=counter;

  497.         tmp_L_reg<=tmp_L;

  498.         tmp_R_reg<=tmp_R;

  499.         tmp_U_reg<=tmp_U;

  500.     end

  501. end

  502. 

  503. //Combinational Logic - FSM Next State Logic

  504. always_comb 

  505. begin  

  506.   if(in_valid)

  507.     case(c_state)

  508.     idle:       begin 

  509.                    depth=0; node=0;

  510.                    //counter=0; 

  511.                    tmp_L=0; tmp_R=0; tmp_U=0;

  512.                    ena_L=0;wea_L=0;enb_L=0;

  513.                    ena_v=0;wea_v=0; enb_v=0;

  514.                     if(out_valid)

  515.                         n_state=idle;

  516.                     else

  517.                         n_state=root;    

  518.                 end

  519.           

  520.     root:       begin

  521.                   depth=depth_reg;node=node_reg;

  522.                   ena_L=1'b1;wea_L=1'b1;enb_L=0;

  523.                   ena_v=0;wea_v=0; enb_v=0;     

  524.                   for(int k=0; k<N; k++)

  525.                   L_in[k]=y[k];

  526.                   n_state=wait_L_logic;

  527.                 end

  528.    wait_L_logic: 

  529.                 begin

  530.                  depth=depth_reg+1'b1; node=((2*node_reg)+1'b1); tmp_L=0;

  531.                  ena_L=0;wea_L=0;enb_L=1'b1;

  532.                  ena_v=0;wea_v=0; enb_v=0; 

  533.                 

  534.                  n_state=wait_L;

  535.                 end

  536.     wait_L:    begin

  537. //                 if(counter==cmax) begin

  538. //                  counter=counter_reg-cmax;

  539.                   n_state=state_L; 

  540. //                 end

  541. //                 else

  542. //                  counter=counter_reg+1;

  543.                end

  544.     state_L:    begin     

  545.                     ena_L=1'b1;wea_L=1'b1;enb_L=0;

  546.                     ena_v=0;wea_v=0; enb_v=0;

  547.                     tmp_L=tmp_L_reg+1'b1;

  548.                     temp_index_f=((N/(2**(depth+1'b1)))*((2*(node)+1'b1)-((2**(depth+1'b1))-1'b1))); 

  549.                     jL1=(tmp_L_reg)+temp_index_f;

  550.                     jL2=(tmp_L_reg)+temp_index_f+(N/(2**depth));

  551.                     fminsum_calc(L_out[jL1],L_out[jL2],L_in[jL1]); 

  552.                                                                

  553.                     if(tmp_L< (N/(2**depth)))    

  554.                         n_state=state_L;                 

  555.                     else if(depth<d)

  556.                         n_state=wait_L_logic;

  557.                     else

  558.                         n_state=wait_LRU_logic;

  559.                 end

  560. 

  561.      wait_R_logic: begin

  562.                     depth=depth_reg-1'b1; node=node_reg+1'b1; tmp_R=0;

  563.                     n_state=wait_R;

  564.                    end                       

  565.      wait_R:      begin

  566.                     ena_L=0;wea_L=0;enb_L=1'b1;

  567.                     ena_v=0;wea_v=0; enb_v=1'b1; 

  568. //                    if(counter==cmax) begin

  569. //                    counter=counter_reg-cmax;

  570.                     n_state=state_R; 

  571. //                    end

  572. //                    else

  573. //                    counter=counter_reg+1;

  574.                  end                       

  575.     

  576.     state_R:    begin 

  577.                    ena_L=1'b1;wea_L=1'b1;enb_L=0;

  578.                    ena_v=0;wea_v=0; enb_v=0;

  579.                    tmp_R=tmp_R_reg+1'b1;

  580.                    temp_index_f=((N/(2**(depth+1'b1)))*((2*(node)+1'b1)-((2**(depth+1'b1))-1'b1)));

  581.                    temp_index_g=((N/(2**(depth+1'b1)))*((2*(node-1'b1)+1'b1)-((2**(depth+1'b1))-1'b1)));

  582.                    jR1=(tmp_R_reg)+temp_index_g;

  583.                    jR2=(tmp_R_reg)+temp_index_g+(N/(2**depth));

  584.                    jR3=(tmp_R_reg)+temp_index_f;

  585.                    g_calc(L_out[jR1],L_out[jR2],v_out[jR1],L_in[jR3]);

  586.                       

  587.                    if(tmp_R< (N/(2**depth)))    

  588.                        n_state=state_R;

  589.                    else if(node==((2**d)-2)) 

  590.                        n_state=wait_lnode_logic;

  591.                    else if(depth==d)

  592.                        n_state=wait_LRU_logic;

  593.                    else 

  594.                        n_state = wait_L_logic;                                               

  595.                end                   

  596.                             

  597.      wait_U_logic: begin

  598. //                     depth=depth_reg-1'b1; node=(node_reg-2)/2; tmp_U=0;

  599.                      depth=depth_reg-1'b1; node=(node_reg-2)>>1; tmp_U=0;

  600.                      n_state=wait_U;

  601.                    end                       

  602.      wait_U:     begin

  603.                      ena_L=0;wea_L=0;enb_L=0;

  604.                      ena_v=0;wea_v=0; enb_v=1'b1; 

  605. //                     if(counter==cmax) begin

  606. //                     counter=counter_reg-cmax;

  607.                      n_state=state_U; 

  608. //                     end

  609. //                     else

  610. //                     counter=counter_reg+1;

  611.                  end                        

  612.     state_U:    begin

  613.                      ena_L=0;wea_L=0;enb_L=0;

  614.                      ena_v=1'b1;wea_v=1'b1; enb_v=0;

  615.                      tmp_U=tmp_U_reg+1'b1;

  616.                      temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1))); 

  617.                      jU1=(tmp_U_reg)+temp_index_f;

  618.                      jU2=(tmp_U_reg)+temp_index_f+(N/(2**(depth)));

  619.                      v_in[jU1] = v_out[jU1] ^ v_out[jU2]; 

  620.                      v_in[jU2] = v_out[jU2]; 

  621.                                     

  622.                      if(tmp_U<(N/(2**(depth)))) 

  623.                          n_state=state_U;

  624.                      else if(depth>0 && ~node[0])  

  625.                          n_state = wait_U_logic;                          

  626.                      else if(depth>0 && node!=0)

  627.                          n_state=wait_R_logic;

  628.                      else              

  629.                          n_state=wait_lstate_logic;         

  630.                   end 

  631.     wait_LRU_logic: begin

  632. //                     depth=depth_reg; node=(node_reg-1'b1)/2;

  633.                      depth=depth_reg; node=(node_reg-1'b1)>>1;

  634.                       n_state=wait_LRU;

  635.                     end                         

  636.     wait_LRU:   begin

  637.                     ena_L=0;wea_L=0;enb_L=1'b1;

  638.                     ena_v=0;wea_v=0; enb_v=0; 

  639. //                    if(counter==cmax) begin

  640. //                    counter=counter_reg-cmax;

  641.                     n_state=state_LRU; 

  642. //                    end

  643. //                    else

  644. //                    counter=counter_reg+1;

  645.                 end                                                            

  646.  

  647.     state_LRU:  begin

  648.                     ena_L=0;wea_L=0;enb_L=0;

  649.                     ena_v=1'b1;wea_v=1'b1; enb_v=0;

  650.                     temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1)));

  651.                     fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);

  652. //                    u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0);

  653.                     u[(2*node)+2-N]=(f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1 : 0);

  654.                     g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);

  655.                     //u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0);

  656.                     u[(2*node)+3-N]=(f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1 : 0);

  657.                     v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N];

  658.                     v_in[temp_index_f+1]=u[(2*node)+3-N];                                                       

  659.                     

  660. //                    if(node[0]==1)               

  661.                     if(node[0])               

  662.                         n_state = wait_R_logic;                                 

  663.                     else                          

  664.                         n_state=wait_U_logic;

  665.                     end  

  666.     wait_lnode_logic:  begin

  667.                          depth=depth_reg+1'b1; node=node_reg;

  668.                          n_state=wait_lnode;

  669.                        end                         

  670.     wait_lnode:        begin

  671.                          ena_L=0;wea_L=0;enb_L=1'b1;

  672.                          ena_v=0;wea_v=0; enb_v=0; 

  673. //                         if(counter==cmax) begin

  674. //                         counter=counter_reg-cmax;

  675.                          n_state=state_lnode; 

  676. //                         end

  677. //                         else

  678. //                         counter=counter_reg+1;

  679.                        end 

  680.      state_lnode:      begin  

  681.                          ena_L=0;wea_L=0;enb_L=0;

  682.                          ena_v=1'b1;wea_v=1'b1; enb_v=0;

  683.                          temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1)));

  684.                          fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]);

  685.  //                        u[(2*node)+2-N]=(f[(2*node)+2-N]==1'b1) ? 0 : ((LRU[0][BITS-1] == 1'b1) ? 1'b1 : 0);

  686.                          u[(2*node)+2-N]=(f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1'b1 : 0);

  687.                          g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]);

  688. //                         u[(2*node)+3-N]=(f[(2*node)+3-N]==1'b1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1'b1 : 0);   

  689.                          u[(2*node)+3-N]=(f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1'b1 : 0);   

  690.                          v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N];

  691.                          v_in[temp_index_f+1]=u[(2*node)+3-N];                                                    

  692.                          n_state = wait_U_logic; 

  693.                        end 

  694.      wait_lstate_logic: begin

  695.                          depth=depth_reg;  node=node_reg;

  696.                          n_state=wait_lstate;

  697.                         end                         

  698.      wait_lstate:       begin

  699.                           ena_L=0;wea_L=0;enb_L=1'b1;

  700.                           ena_v=0;wea_v=0; enb_v=0; 

  701. //                          if(counter==cmax) begin

  702. //                          counter=counter_reg-cmax;

  703.                           n_state=state_last; 

  704. //                          end

  705. //                          else

  706. //                          counter=counter_reg+1;

  707.                         end

  708.      state_last:       begin

  709.                           ena_L=0;wea_L=0;enb_L=0;

  710.                           ena_v=1'b1;wea_v=1'b1; enb_v=0;

  711.                           v=v_out;

  712.                           n_state=idle;

  713.                         end                                            

  714.     endcase  

  715. else    n_state = idle;                    

  716. end

  717. endmodule