`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 03/03/2021 12:49:56 PM
// Design Name: 
// Module Name: bram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module bram_v #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256)(
input wire clk,ena,enb,wea,
input wire [ADDR_WIDTH-1:0]addra, addrb,
input wire [DATA_WIDTH-1:0]dia,
output reg [DATA_WIDTH-1:0]dob
);
(*ram_style="block"*)reg [DATA_WIDTH-1:0]ram[0:DEPTH-1];
always@(posedge clk) 
    begin
    if (ena) 
        begin
        if (wea)
        ram[addra] <=dia;
        end
    end
always @(posedge clk) 
    begin
   if (enb) 
        dob <= ram[addrb];
    end
endmodule