diff --git a/sources_1/imports/Downloads/sc_decoder_fsm.sv b/sources_1/imports/Downloads/sc_decoder_fsm.sv index 1f3ff92..09909ca 100644 --- a/sources_1/imports/Downloads/sc_decoder_fsm.sv +++ b/sources_1/imports/Downloads/sc_decoder_fsm.sv @@ -1,4 +1,4 @@ -`timescale 1ns / 1ns +/*`timescale 1ns / 1ns ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: @@ -30,37 +30,47 @@ output logic out_valid ); -//function for fminsum calculation +// Function to calculate f(r1,r2) = sgn(r1) * sgn(r2) * min(|r1|,|r2|) function void fminsum_calc; - input signed [`BITS-1:0] a; - input signed [`BITS-1:0] b; - output signed [`BITS-1:0] c; + input signed [`BITS-1:0] a; + input signed [`BITS-1:0] b; + output signed [`BITS-1:0] c; logic [`BITS-2:0] abs_a; logic [`BITS-2:0] abs_b; logic [`BITS-2:0] abs_c; - - abs_a = (a[`BITS-1] == 1) ? ~a[`BITS-2:0] + 1 : a[`BITS-2:0]; - abs_b = (b[`BITS-1] == 1) ? ~b[`BITS-2:0] + 1 : b[`BITS-2:0]; + + // Mod value of a and b + abs_a = (a[`BITS-1]) ? ~a[`BITS-2:0] + 1'b1 : a[`BITS-2:0]; + abs_b = (b[`BITS-1]) ? ~b[`BITS-2:0] + 1'b1 : b[`BITS-2:0]; + + // Multiplication of sign i.e. XOR c[`BITS-1] = a[`BITS-1] ^ b[`BITS-1]; + + // Minimum value between a and b abs_c = (abs_b < abs_a) ? abs_b : abs_a; - c[`BITS-2:0] = (c[`BITS-1] == 1) ? ~abs_c + 1 : abs_c; - endfunction + // Final Minsum of a and b + c[`BITS-2:0] = (c[`BITS-1]) ? ~abs_c + 1'b1 : abs_c; + +endfunction -//function for g-value calculation - function void g_calc; - input signed [`BITS-1:0] a; + +// Function to Calculate g(r1,r2,u) = r2 + ((1-2u) * r1) +function void g_calc; + input signed [`BITS-1:0] a; input signed [`BITS-1:0] b; input u; output signed [`BITS:0] c; - c = (u == 0) ? (b + a) : (b + (~a+1)); - endfunction + + // when u == 0 => c = b - a + // When u == 1 => c = b + a + c = u ? (b + (~a+1)) : (b + a) ; +endfunction + //parameters and signals declarations localparam d=$clog2(N); //N=4, d=2(0 & 1) -localparam n=2*N-1; //(2**d)-1; -localparam cmax=0; logic [N-1:0]u; logic [d:0]temp_index_f,temp_index_g; reg signed [BITS-1:0] LRU[2]; @@ -76,7 +86,7 @@ logic [4:0] c_state, n_state; wire [N-1:0]u_cap_1; wire [N-1:0]v_final_1; -wire out_valid_1; +//wire out_valid_1; //Auxiliary registers declarations @@ -115,8 +125,8 @@ for(genvar i=0; i0 && node%2==0) + else if(depth>0 && ~node[0]) n_state = wait_U_logic; else if(depth>0 && node!=0) n_state=wait_R_logic; @@ -645,24 +626,24 @@ begin n_state=wait_lstate_logic; end wait_LRU_logic: begin - depth=depth_reg; node=(node_reg-1)/2; + depth=depth_reg; node=(node_reg-1'b1)/2; n_state=wait_LRU; end wait_LRU: begin - ena_L=0;wea_L=0;enb_L=1; + ena_L=0;wea_L=0;enb_L=1'b1; ena_v=0;wea_v=0; enb_v=0; - if(counter==cmax) begin - counter=counter_reg-cmax; +// if(counter==cmax) begin +// counter=counter_reg-cmax; n_state=state_LRU; - end - else - counter=counter_reg+1; +// end +// else +// counter=counter_reg+1; end state_LRU: begin ena_L=0;wea_L=0;enb_L=0; - ena_v=1;wea_v=1; enb_v=0; - temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1))); + ena_v=1'b1;wea_v=1'b1; enb_v=0; + temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1))); fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]); u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0); g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]); @@ -670,7 +651,7 @@ begin v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N]; v_in[temp_index_f+1]=u[(2*node)+3-N]; - if(node%2==1) + if(node[0]==1) n_state = wait_R_logic; else n_state=wait_U_logic; @@ -682,12 +663,12 @@ begin wait_lnode: begin ena_L=0;wea_L=0;enb_L=1; ena_v=0;wea_v=0; enb_v=0; - if(counter==cmax) begin - counter=counter_reg-cmax; +// if(counter==cmax) begin +// counter=counter_reg-cmax; n_state=state_lnode; - end - else - counter=counter_reg+1; +// end +// else +// counter=counter_reg+1; end state_lnode: begin ena_L=0;wea_L=0;enb_L=0; @@ -708,12 +689,12 @@ begin wait_lstate: begin ena_L=0;wea_L=0;enb_L=1; ena_v=0;wea_v=0; enb_v=0; - if(counter==cmax) begin - counter=counter_reg-cmax; +// if(counter==cmax) begin +// counter=counter_reg-cmax; n_state=state_last; - end - else - counter=counter_reg+1; +// end +// else +// counter=counter_reg+1; end state_last: begin ena_L=0;wea_L=0;enb_L=0; @@ -725,4 +706,3 @@ begin else n_state = idle; end endmodule -*/ \ No newline at end of file