| @@ -382,7 +382,7 @@ endmodule | |||||
| // | // | ||||
| ////////////////////////////////////////////////////////////////////////////////// | ////////////////////////////////////////////////////////////////////////////////// | ||||
| `define BITS 8 | `define BITS 8 | ||||
| module sc_decoder_fsm #(parameter BITS=8, N=11'd32)( | |||||
| module sc_decoder_fsm #(parameter BITS=8, N=11'd128)( | |||||
| input clk, rst, | input clk, rst, | ||||
| input in_valid, | input in_valid, | ||||
| input signed [N-1:0][BITS-1:0] y, | input signed [N-1:0][BITS-1:0] y, | ||||
| @@ -471,7 +471,8 @@ for(genvar i=0; i<N; i++) | |||||
| assign u_cap[i] = u[i]; | assign u_cap[i] = u[i]; | ||||
| end | end | ||||
| assign v_final=v; | assign v_final=v; | ||||
| assign out_valid=(n_state==state_last)?1'b1:1'b0; | |||||
| assign out_valid=(n_state==state_lnode)?1'b1:1'b0; | |||||
| // assign out_valid=(n_state==state_last)?1'b1:1'b0; | |||||
| // Sequential Logic - FSM State and Data Registers | // Sequential Logic - FSM State and Data Registers | ||||
| @@ -527,8 +528,9 @@ begin | |||||
| wait_L_logic: | wait_L_logic: | ||||
| begin | begin | ||||
| depth=depth_reg+1'b1; node=((2*node_reg)+1'b1); tmp_L=0; | depth=depth_reg+1'b1; node=((2*node_reg)+1'b1); tmp_L=0; | ||||
| ena_L=0;wea_L=0;enb_L=1; | |||||
| ena_L=0;wea_L=0;enb_L=1'b1; | |||||
| ena_v=0;wea_v=0; enb_v=0; | ena_v=0;wea_v=0; enb_v=0; | ||||
| n_state=wait_L; | n_state=wait_L; | ||||
| end | end | ||||
| wait_L: begin | wait_L: begin | ||||
| @@ -561,8 +563,8 @@ begin | |||||
| n_state=wait_R; | n_state=wait_R; | ||||
| end | end | ||||
| wait_R: begin | wait_R: begin | ||||
| ena_L=0;wea_L=0;enb_L=1; | |||||
| ena_v=0;wea_v=0; enb_v=1; | |||||
| ena_L=0;wea_L=0;enb_L=1'b1; | |||||
| ena_v=0;wea_v=0; enb_v=1'b1; | |||||
| // if(counter==cmax) begin | // if(counter==cmax) begin | ||||
| // counter=counter_reg-cmax; | // counter=counter_reg-cmax; | ||||
| n_state=state_R; | n_state=state_R; | ||||
| @@ -574,7 +576,7 @@ begin | |||||
| state_R: begin | state_R: begin | ||||
| ena_L=1'b1;wea_L=1'b1;enb_L=0; | ena_L=1'b1;wea_L=1'b1;enb_L=0; | ||||
| ena_v=0;wea_v=0; enb_v=0; | ena_v=0;wea_v=0; enb_v=0; | ||||
| tmp_R=tmp_R_reg+1; | |||||
| tmp_R=tmp_R_reg+1'b1; | |||||
| temp_index_f=((N/(2**(depth+1'b1)))*((2*(node)+1'b1)-((2**(depth+1'b1))-1'b1))); | temp_index_f=((N/(2**(depth+1'b1)))*((2*(node)+1'b1)-((2**(depth+1'b1))-1'b1))); | ||||
| temp_index_g=((N/(2**(depth+1'b1)))*((2*(node-1'b1)+1'b1)-((2**(depth+1'b1))-1'b1))); | temp_index_g=((N/(2**(depth+1'b1)))*((2*(node-1'b1)+1'b1)-((2**(depth+1'b1))-1'b1))); | ||||
| jR1=(tmp_R_reg)+temp_index_g; | jR1=(tmp_R_reg)+temp_index_g; | ||||
| @@ -593,12 +595,13 @@ begin | |||||
| end | end | ||||
| wait_U_logic: begin | wait_U_logic: begin | ||||
| depth=depth_reg-1'b1; node=(node_reg-2)/2; tmp_U=0; | |||||
| // depth=depth_reg-1'b1; node=(node_reg-2)/2; tmp_U=0; | |||||
| depth=depth_reg-1'b1; node=(node_reg-2)>>1; tmp_U=0; | |||||
| n_state=wait_U; | n_state=wait_U; | ||||
| end | end | ||||
| wait_U: begin | wait_U: begin | ||||
| ena_L=0;wea_L=0;enb_L=0; | ena_L=0;wea_L=0;enb_L=0; | ||||
| ena_v=0;wea_v=0; enb_v=1; | |||||
| ena_v=0;wea_v=0; enb_v=1'b1; | |||||
| // if(counter==cmax) begin | // if(counter==cmax) begin | ||||
| // counter=counter_reg-cmax; | // counter=counter_reg-cmax; | ||||
| n_state=state_U; | n_state=state_U; | ||||
| @@ -626,7 +629,8 @@ begin | |||||
| n_state=wait_lstate_logic; | n_state=wait_lstate_logic; | ||||
| end | end | ||||
| wait_LRU_logic: begin | wait_LRU_logic: begin | ||||
| depth=depth_reg; node=(node_reg-1'b1)/2; | |||||
| // depth=depth_reg; node=(node_reg-1'b1)/2; | |||||
| depth=depth_reg; node=(node_reg-1'b1)>>1; | |||||
| n_state=wait_LRU; | n_state=wait_LRU; | ||||
| end | end | ||||
| wait_LRU: begin | wait_LRU: begin | ||||
| @@ -645,23 +649,26 @@ begin | |||||
| ena_v=1'b1;wea_v=1'b1; enb_v=0; | ena_v=1'b1;wea_v=1'b1; enb_v=0; | ||||
| temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1))); | temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1))); | ||||
| fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]); | fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]); | ||||
| u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0); | |||||
| // u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0); | |||||
| u[(2*node)+2-N]=(f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1 : 0); | |||||
| g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]); | g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]); | ||||
| u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0); | |||||
| //u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0); | |||||
| u[(2*node)+3-N]=(f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1 : 0); | |||||
| v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N]; | v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N]; | ||||
| v_in[temp_index_f+1]=u[(2*node)+3-N]; | v_in[temp_index_f+1]=u[(2*node)+3-N]; | ||||
| if(node[0]==1) | |||||
| // if(node[0]==1) | |||||
| if(node[0]) | |||||
| n_state = wait_R_logic; | n_state = wait_R_logic; | ||||
| else | else | ||||
| n_state=wait_U_logic; | n_state=wait_U_logic; | ||||
| end | end | ||||
| wait_lnode_logic: begin | wait_lnode_logic: begin | ||||
| depth=depth_reg+1; node=node_reg; | |||||
| depth=depth_reg+1'b1; node=node_reg; | |||||
| n_state=wait_lnode; | n_state=wait_lnode; | ||||
| end | end | ||||
| wait_lnode: begin | wait_lnode: begin | ||||
| ena_L=0;wea_L=0;enb_L=1; | |||||
| ena_L=0;wea_L=0;enb_L=1'b1; | |||||
| ena_v=0;wea_v=0; enb_v=0; | ena_v=0;wea_v=0; enb_v=0; | ||||
| // if(counter==cmax) begin | // if(counter==cmax) begin | ||||
| // counter=counter_reg-cmax; | // counter=counter_reg-cmax; | ||||
| @@ -672,12 +679,14 @@ begin | |||||
| end | end | ||||
| state_lnode: begin | state_lnode: begin | ||||
| ena_L=0;wea_L=0;enb_L=0; | ena_L=0;wea_L=0;enb_L=0; | ||||
| ena_v=1;wea_v=1; enb_v=0; | |||||
| temp_index_f=((N/(2**(depth)))*((2*node+1)-((2**(depth))-1))); | |||||
| ena_v=1'b1;wea_v=1'b1; enb_v=0; | |||||
| temp_index_f=((N/(2**(depth)))*((2*node+1'b1)-((2**(depth))-1'b1))); | |||||
| fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]); | fminsum_calc(L_out[temp_index_f],L_out[temp_index_f+1],LRU[0]); | ||||
| u[(2*node)+2-N]=(f[(2*node)+2-N]==1) ? 0 : ((LRU[0][BITS-1] == 1) ? 1 : 0); | |||||
| // u[(2*node)+2-N]=(f[(2*node)+2-N]==1'b1) ? 0 : ((LRU[0][BITS-1] == 1'b1) ? 1'b1 : 0); | |||||
| u[(2*node)+2-N]=(f[(2*node)+2-N]) ? 0 : ((LRU[0][BITS-1]) ? 1'b1 : 0); | |||||
| g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]); | g_calc(L_out[temp_index_f],L_out[temp_index_f+1],u[(2*node)+2-N],LRU[1]); | ||||
| u[(2*node)+3-N]=(f[(2*node)+3-N]==1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1 : 0); | |||||
| // u[(2*node)+3-N]=(f[(2*node)+3-N]==1'b1) ? 0 : ((LRU[1][BITS-1] == 1) ? 1'b1 : 0); | |||||
| u[(2*node)+3-N]=(f[(2*node)+3-N]) ? 0 : ((LRU[1][BITS-1]) ? 1'b1 : 0); | |||||
| v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N]; | v_in[temp_index_f]=u[(2*node)+2-N] ^ u[(2*node)+3-N]; | ||||
| v_in[temp_index_f+1]=u[(2*node)+3-N]; | v_in[temp_index_f+1]=u[(2*node)+3-N]; | ||||
| n_state = wait_U_logic; | n_state = wait_U_logic; | ||||
| @@ -687,7 +696,7 @@ begin | |||||
| n_state=wait_lstate; | n_state=wait_lstate; | ||||
| end | end | ||||
| wait_lstate: begin | wait_lstate: begin | ||||
| ena_L=0;wea_L=0;enb_L=1; | |||||
| ena_L=0;wea_L=0;enb_L=1'b1; | |||||
| ena_v=0;wea_v=0; enb_v=0; | ena_v=0;wea_v=0; enb_v=0; | ||||
| // if(counter==cmax) begin | // if(counter==cmax) begin | ||||
| // counter=counter_reg-cmax; | // counter=counter_reg-cmax; | ||||
| @@ -698,7 +707,7 @@ begin | |||||
| end | end | ||||
| state_last: begin | state_last: begin | ||||
| ena_L=0;wea_L=0;enb_L=0; | ena_L=0;wea_L=0;enb_L=0; | ||||
| ena_v=1;wea_v=1; enb_v=0; | |||||
| ena_v=1'b1;wea_v=1'b1; enb_v=0; | |||||
| v=v_out; | v=v_out; | ||||
| n_state=idle; | n_state=idle; | ||||
| end | end | ||||