PBCH_ENCODER/PBCH_POLAR_ENCODER_IP.sv

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BITSILICA PVT LTD
// Design Name:PBCH_POLAR_ENCODER_IP 
// Module Name: PBCH_POLAR_ENCODER_IP
// Project Name: POLAR IP
// Description: The PBCH_POLAR_ENCODER IP is interfaced with AXI4 Stream DIN
// Slave and DOUT Master interfaces. 
//////////////////////////////////////////////////////////////////////////////////
`include "PBCH_Defines.vh"

`define Dx_WIDTH        32      // Dx_WIDTH     => DIN_WIDTH / DOUT_WIDTH  => AXI4-Stream Interface   
`define PDCCH           0


module PBCH_POLAR_ENCODER_IP(

/**************************************************************/    
//              Global Signals
    input  logic                        reset_n,    // Active Low Reset
    input  logic                        core_clk,   // Core Clock

/**************************************************************/    
//              AXI4 DIN Stream Interface 
    input  logic [`Dx_WIDTH - 1 : 0]    s_axis_din_tdata,
    input  logic                        s_axis_din_tvalid,
    input  logic                        s_axis_din_tlast,
    output logic                        DIN_TREADY,
    
/**************************************************************/        
//              AXI4 DOUT Stream Interface 
    input  logic                        s_axis_dout_tready,
    output logic [`Dx_WIDTH - 1 : 0]    DOUT_TDATA,
    output logic                        DOUT_TVALID,
    output logic                        DOUT_TLAST
                        
 
);
   
    logic [`Dx_WIDTH - 1 : 0]   m_axis_din_tdata;
    logic [`G - 1 : 0]          msg_o;
    logic [9:0]                 global_count;
    logic                       done;    

S_AXIS #
	(.C_S_AXIS_TDATA_WIDTH(`Dx_WIDTH)
	) DIN_STREAM
	(.S_AXIS_ACLK(core_clk),
	 .S_AXIS_ARESETN(reset_n),
	 .S_AXIS_TREADY(DIN_TREADY),
	 .M_AXIS_TDATA(m_axis_din_tdata),      // Output from Stream
	 .S_AXIS_TDATA(s_axis_din_tdata),      // Input from Stream
	 .S_AXIS_TLAST(s_axis_din_tlast),
	 .S_AXIS_TVALID(s_axis_din_tvalid),
	 .tready_in(done)
	);
	
 POLAR_ENCODER  
   #(.PBCH(`PBCH),              // Broadcast Channel enable
     .A(`A),                    // Message width A if no segmentation needed, A'=A/2 if segmentation is needed.
     .G(`G)                     // Length of output
   ) PBCH
    (.clock_i(core_clk),        // input clock signal
     .reset_ni(reset_n),        // input reset
     .msg_i(m_axis_din_tdata),  // input message bits
     .msg_o(msg_o)              // output bits
   );
  
   always_ff@(posedge core_clk)
    if(!reset_n)
      global_count <= 0;
    else if(global_count <= 'd525)
      global_count <= global_count + 1'b1;
    else
      global_count <= 0; 
      
            
   assign done = (reset_n == 0)||(global_count =='d524) ? 1'b1 : 1'b0;

DOUT_M_AXIS #
	(
		// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
		.C_M_AXIS_TDATA_WIDTH(`Dx_WIDTH),
		.C_S_AXIS_TDATA_WIDTH(`G),
		.DEPTH(27),
		.C_M_START_COUNT(2)) DOUT_STREAM
	(
		// Global ports
		.M_AXIS_ACLK(core_clk),
		.M_AXIS_ARESETN(reset_n),
		// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. 
		.M_AXIS_TVALID(DOUT_TVALID),
		// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
		.M_AXIS_TDATA(DOUT_TDATA),
		// TLAST indicates the boundary of a packet.
		.M_AXIS_TLAST(DOUT_TLAST),
		// TREADY indicates that the slave can accept a transfer in the current cycle.
		.M_AXIS_TREADY(s_axis_dout_tready),
		// Input from PBCH Encoder Core of Width 864 bits 
        .S_AXIS_TDATA(msg_o),
		// Input from PBCH Encoder Core
		.DONE(done)		
	);

endmodule