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- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company: BITSILICA PRIVATE LIMITED
- //
- // Design Name: POLAE_ENCODER
- // Module Name: POLAR_ENCODER
- // Project Name: POLAR ENCODER-DECODER
- // Target Devices: Zynq UltraScale+ ZCU111 Evaluation Platform (xczu28dr-ffvg1517-2-e)
- // Tool Versions: VIVADO 2020.1
- // Description: RTL code for integration of all sub blocks of polar encoder
- //////////////////////////////////////////////////////////////////////////////////
-
- module POLAR_ENCODER
- #(
- parameter PUCCH=0, // Uplink Channel enable
- parameter PBCH=1, // Broadcast Channel enable
- parameter A=32, // Message width A if no segmentation needed, A'=A/2 if segmentation is needed.
- parameter P=24,
- parameter G=864, // Length of output
- parameter C=1, // Value of C=2 if segmentation need to be done otherwise C=1
-
- parameter E=G/C, // Value of E based on G and C
- parameter K=A+P, // Length of information+CRC width
- parameter n_min=5,
- parameter n_max=9,
- parameter n_1= ((E<=((9/8)*(2**(($clog2(E))-1))))&&((K/E)<(9/16)))? ($clog2(E)-1) : $clog2(E),
- parameter n_2= $clog2(8*K),
- parameter min_n1_n2= (n_1 >= n_2)? n_2 : n_1,
- parameter min_n1_n2_nmax = (min_n1_n2 >= n_max) ? n_max : min_n1_n2 ,
- parameter n=(min_n1_n2_nmax >= n_min)? min_n1_n2_nmax : n_min,
- parameter N=2**n,
-
- parameter ITLV=1, // Interleave flag for CRC interleaving process
- parameter KMAX=164 // Maximum value of K for CRC interleaving
- )
- (
- input clock_i, // input clock signal
- input reset_ni, // input reset
- input wire [A-1:0] msg_i, // input message bits
- output reg [G-1:0] msg_o // output bits
- );
-
- wire [K-1:0] msg_1; // output of CRC attachment
- wire [K-1:0] msg_2; // output of CRC scrambling
- wire [K-1:0] msg_x; // output of CRC interleaving
- wire [N-1:0] msg_3; // output of frozen insertion
- wire [N-1:0] msg_4; // output of encoder core
- wire [N-1:0] msg_5; // output of sub block interleaving
- wire [G-1:0] msg_6; // output of bit selection
-
-
- if(PBCH) begin
- encoder_crc_attachment_rtl #(
- .PUCCH( PUCCH ), // Uplink Channel enable
- .PBCH( PBCH ), // Broadcast Channel enable
- .A(A), // Message width A if no segmentation needed, A'=A/2 if segmentation is needed.
- .N(N)
- ) ENCODER_PBCH_CRC_ATTACHMENT (
- .clock_i(clock_i), // System clock
- .reset_ni(reset_ni), // System reset,active low synchronous
- .msg_i( msg_i), // Input message bits
- .msg_o( msg_1) // total message = message input + CRC bits
- );
-
- encoder_crc_interleaving_rtl#(
- .K(K),
- .ITLV(ITLV),
- .KMAX(KMAX)
- ) ENCODER_PBCH_CRC_INTERLEAVING (
- .clock_i(clock_i), // system clock
- .reset_ni(reset_ni), // active low, synchronous reset
- .msg_i( msg_1), // input message to be interleaved
- .msg_o( msg_2) // output crc interleaved message
- );
-
- encoder_frozen_bit_insertion_rtl1 #(
- .N(N), // length of information+CRC+Frozen bits
- .K(K) // length of information+CRC bits
- ) ENCODER_PBCH_FROZEN_INSERTION (
- .clock_i(clock_i), // system clock
- .reset_ni(reset_ni), // active low synchronous reset
- .msg_i( msg_2), // input information+CRC bits
- .msg_o(msg_3) // information+CRC+frozen bits
- );
-
- encoder_core_rtl #(
- .N(N) // length of input and output messages for encoder_core_rtl
- ) ENCODER_PBCH_CORE (
- .clock_i(clock_i), // system clock
- .reset_ni(reset_ni), // active low, synchronous reset
- .msg_i( msg_3), // input message to be encoded
- .msg_o(msg_4) // output encoded codeword
- );
-
-
- encoder_sub_block_interleaving_rtl #(
- .N( N) // input and output sequence length
- ) ENCODER_PBCH_SUB_BLOCK_INTERLEAVING (
- .clock_i(clock_i),
- .reset_ni(reset_ni),
- .msg_i(msg_4), // input message for sub block interleaver
- .msg_o(msg_5) // output message after sub block interleaving
- );
-
- encoder_bit_selection_rtl #(
- .K(K),
- .G(G),
- .C(C),
- .E(E),
- .N(N)
- ) ENCODER_PBCH_BIT_SELECTION (
- .clock_i(clock_i), // system clock
- .reset_ni(reset_ni), // active low, synchronous reset
- .msg_i(msg_5), // input message for bit selection
- .msg_o(msg_6) // output message after bit selection
- );
- end
-
- always@(posedge clock_i) // registering output with respect to clock
- if(!reset_ni)
- msg_o <=0;
- else
- begin
- msg_o <=msg_6;
- end
- endmodule
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