|
- `timescale 1ns / 1ps
-
- //////////////////////////////////////////////////////////////////////////////////
- // Company: BITSILICA PRIVATE LIMITED
- // Design Name: ENCODER BIT SELECTION
- // Module Name: encoder_bit_selection_rtl
- // Project Name: POLAR ENCODER-DECODER
- // Target Devices: Zynq UltraScale+ ZCU111 Evaluation Platform (xczu28dr-ffvg1517-2-e)
- // Tool Versions: VIVADO 2020.1
- // Description: RTL code for bit selection, in order to change the length of a sequence from N to E,
- // also known as rate matching.
- //
- //
- //////////////////////////////////////////////////////////////////////////////////
- module encoder_bit_selection_rtl
- #(
- parameter K = 164,
- parameter G = 1728,
- parameter C = 1,
- parameter E = G/C,
- parameter N=512
- )
- (
- input wire clock_i, // system clock
- input wire reset_ni, // active low synchronous reset
- input wire [N-1:0] msg_i, // input message for bit selection
- output reg [E-1:0] msg_o // output message bit selection
- );
-
- localparam Y = E/N;
- localparam Z = E%N;
-
- integer i;
-
- generate
- always@(posedge clock_i) begin
- if(!reset_ni )begin
- msg_o <= 0;
- end
- else begin
- if(E>=N)
- begin
- for(i = 1;i <= Y;i = i+1) // Repitition //
- msg_o[((i*N)-1) -: N]<=msg_i[N-1:0]; // Assigning same N bits to output reg for E/N times
- if(Z != 0)begin
- msg_o[E-1:N*(Y)] <= msg_i[Z-1:0]; // Assingning remaining E%N bits
- end
- end
- else
- begin
- if((10000*(K/E)) <= (70000/16)) // Puncturing //
- msg_o[E-1:0] <= msg_i[N-1:N-E]; // Assigning last E bits to output register
- else // Shortening //
- msg_o[E-1:0] <= msg_i[E-1:0]; // Assigning first E bits to output register
- end
- end
- end
- endgenerate
-
- endmodule
|