`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BITSILICA PVT LTD
// Design Name: 
// Module Name: simple_dual_port_ram
// Project Name: 
//////////////////////////////////////////////////////////////////////////////////


module simple_dual_port_ram#(parameter WIDTH = 32, DEPTH = 16,AW = 4)(clk,enb,wea,addra,addrb,dia,dob);
    
    input                clk,wea,enb;
    input   [AW    -1:0] addra,addrb;
    input   [WIDTH -1:0] dia;
    output  [WIDTH -1:0] dob;
    reg     [WIDTH -1:0] dob;

    reg     [WIDTH -1:0] ram [DEPTH -1:0];

    always @(posedge clk) begin
     if (wea)
     ram[addra] <= dia;
    end
    always @(posedge clk) begin 
    if (enb)
     dob <= ram[addrb];
    end
   endmodule