`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BITSILICA PRIVATE LIMITED
// Design Name: ENCODER SUB-BLOCK INTERLEAVING
// Module Name: encoder_sub_block_interleaving_rtl
// Project Name: POLAR ENCODER-DECODER
// Target Devices: Zynq UltraScale+ ZCU111 Evaluation Platform (xczu28dr-ffvg1517-2-e)
// Tool Versions: VIVADO 2020.1
// Description: RTL code for sub block interleaving, in order to interleave the sub blocks of encoded codeword.
//
//////////////////////////////////////////////////////////////////////////////////

module encoder_sub_block_interleaving_rtl#(
  parameter N=512                   // input and output sequence length
                                    // parameter to break down the input message into 32- sub blocks of euqal length, S=N/32
) (
  input  wire          clock_i,
  input  wire          reset_ni,
  input  wire  [N-1:0] msg_i,       // input message for sub block interleaver
  output  reg  [N-1:0] msg_o        // output message after sub block interleaving
);
	
  localparam S=(N >> 3'd5);         // parameter to break down the input message into 32- sub blocks of euqal length, S=N/32

  reg   [4:0] sbi_pat [31:0] = '{5'd31, 5'd30, 5'd29, 5'd27, 
                                 5'd28, 5'd26,5'd25, 5'd24, 
                                 5'd23,5'd15,5'd22, 5'd14, 
                                 5'd21, 5'd13, 5'd20, 5'd12, 
                                 5'd19, 5'd11, 5'd18, 5'd10, 
                                 5'd17, 5'd9, 5'd16, 5'd8, 
                                 5'd7, 5'd6, 5'd5, 5'd3, 
                                 5'd4, 5'd2, 5'd1, 5'd0};                           
  logic [N-1:0] msg_1;
  logic         sub_blocks [31:0] [S-1:0];       //register to store the sub divided blocks
  logic         temp       [31:0] [S-1:0];       //register to store the interleaved sub blocks
    
  integer i,j,k,p,q,r;                           //looping variables

  // instantiating a register(group of FF's) to hold the output and synchronize the module w.r.t clock and reset signals
  register #(
    .WIDTH(N),                       // overriding the width of register with the length of output to be registered  
    .SR(2'b00),                      // overriding SR inputs of the register
    .RST_VAL({N{1'b0}})              // overriding the reset value with expected value in the output when reset is applied
  ) REG (
    .clk(clock_i),                   // connecting clock ports
    .rstb(reset_ni),                 // connecting reset ports
    .din(msg_1),                     // connecting input of register with the value that needs to be registered
    .dout(msg_o)                     // connecting the registered output with the output port of current module
  );

  always_comb begin
  //breaking down the message into 32 bit sub blocks of width N/32
    begin
      for(j = 0 ; j < 32 ; j=j+1) begin
        for (i = 0 ; i < S ; i = i+1) begin
		    sub_blocks[j][i] = msg_i[(j*S)+i];
		end
	end
  end
	 
  //interleaving the subblocks according to the interleaving pattern	 
    begin
      for(p = 0 ; p < 32 ; p = p+1) begin
        temp[p] = sub_blocks[sbi_pat[p]];
      end
    end
	 
  //assigning interleaved bits to the output
    begin
      for(q = 0 ; q < 32 ; q = q+1) begin
        for (r = 0 ; r < S ; r = r+1) begin
          msg_1[(q*S)+r] = temp[q][r];
        end
      end
    end
  end
  
endmodule