`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: BITSILICA PRIVATE LIMITED
// Design Name: ENCODER CORE
// Module Name: encoder_core_rtl
// Project Name: POLAR ENCODER-DECODER
// Target Devices: Zynq UltraScale+ ZCU111 Evaluation Platform (xczu28dr-ffvg1517-2-e)
// Tool Versions: VIVADO 2020.1
// Description: RTL code for polar encoder core operation.
// 
// encoder_core_rtl is written to encode an N-bit input message and produce an N-bit 
// encoded codeword as an output
// 
//////////////////////////////////////////////////////////////////////////////////

module encoder_core_rtl 
#(
  parameter  N = 512,                // length of input and output messages for encoder_core_rtl
  localparam DEPTH = $clog2(N)       // to derive depth of binary tree to carry out the operation of polar encoder core
  )
 (
  input  wire         clock_i,       // system clock
  input  wire         reset_ni,      // active low, synchronous reset
  input  wire [N-1:0] msg_i,         // input message to be encoded
  output reg  [N-1:0] msg_o          // output encoded codeword
);

  reg    [N-1:0] msg_1;              // internal register to hold the encoded codeword throughout the operation 
  integer i,j,k;                     // looping variables
  
  // instantiating a register(group of FF's) to hold the output and synchronize the module w.r.t clock and reset signals
  register #(
    .WIDTH(N),                       // overriding the width of register with the length of output to be registered  
    .SR(2'b00),                      // overriding SR inputs of the register
    .RST_VAL({N{1'b0}})              // overriding the reset value with expected value in the output when reset is applied
  ) REG (
    .clk(clock_i),                   // connecting clock ports
    .rstb(reset_ni),                 // connecting reset ports
    .din(msg_1),                     // connecting input of register with the value that needs to be registered
    .dout(msg_o)                     // connecting the registered output with the output port of current module
  );
  
  // combinational always block for performing encoder operation
  always_comb begin
    msg_1 = msg_i;                                                    // temporary register is fed with input message
      for (i = 0; i <= DEPTH; i = i+1) begin : depth                  // to loop through the depth of binary tree
        for (j = 0; j <= (N-(2 ** i)); j = j+(2 ** i)) begin : limit  // to find the boundaries of bits in different depths
          for (k = j; k < (j+(2 ** (i-1))); k = k+1) begin : count    // to find the number of xor operations required to encode the message
            msg_1[k] = msg_1[k] ^ msg_1[k + (2 ** (i-1))];            // xor between two particular bits to be stored in another bit, based on the index calculated
          end : count
        end : limit
      end : depth
  end 
		
endmodule