|
123456789101112131415161718192021222324252627282930313233343536373839404142434445 |
- `timescale 1ns / 1ps
- //////////////////////////////////////////////////////////////////////////////////
- // Company: BITSILICA PRIVATE LIMITED
- //
- // Design Name: Register
- // Module Name: register
- // Project Name: POLAR ENCODER-DECODER
- // Tool Versions: VIVADO 2020.1
- //////////////////////////////////////////////////////////////////////////////////
-
- // register is written to synchronize a combiational logic w.r.t clock and reset signals
- module register #(
- parameter int WIDTH = 1, // width of the input and output of the register
- parameter logic [1:0] SR = 2'b00, // SET and RESET inputs of the register
- parameter logic [WIDTH-1:0] RST_VAL = {WIDTH{1'b0}} // reset value to be provided at the output when reset signal is active
- ) (
- input logic clk, // clock signal for register
- input logic rstb, // active low, synchronous reset
- input logic [WIDTH-1:0] din, // input to be registered
- output logic [WIDTH-1:0] dout // registered outputs
- );
-
- generate
- if(SR==2'b00) begin : NON_RESET_FLOP // if SR==00, irrespective of other signals the input needs to be registered
- always_ff @ (posedge clk) begin
- dout <= din; // registering input w.r.t posedge of clock signal
- end
- end : NON_RESET_FLOP
- else begin: RESET_FLOP // if SR!==00, input needs to be registered according to other signals w.r.t posedge of clock signal
- always_ff @ (posedge clk ) begin
- if (~rstb) // if reset is active
- if (SR == 2'b01)
- dout <= {WIDTH{1'b0}}; // if SR==01, reset the output
- else if (SR == 2'b10)
- dout <= {WIDTH{1'b1}}; // if SR==10, set the output
- else
- dout <= RST_VAL; // if SR==11, reset the output according the reset value provided
- else
- dout <= din; // if reset is inactive, register the input
- end
- end: RESET_FLOP
- endgenerate
-
- endmodule
-
|