commit 5b82fdee1ded8315666bb63d35bc9db9cbf7657b
Author: amit.b <amit.b@bitsilica.com>
Date:   Thu Mar 4 19:23:18 2021 +0530

    CRC24 with data_input width of 140

diff --git a/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv b/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv
new file mode 100644
index 0000000..7552760
--- /dev/null
+++ b/encoder_crc_attachment.srcs/sources_1/new/crc_gen.sv
@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+
+          
+module crc_gen #(
+            parameter int          CRC_SIZE   = 24,
+            parameter int          DATA_WIDTH = 140,
+            parameter bit [63 : 0] INIT       = 'h0
+          )(
+            input                           clk_i,
+            input                           rst_n,
+            input  [24:0]                   POLY,               
+            input  [DATA_WIDTH - 1 : 0]     data_i,           // Input Information bit 
+            output reg [CRC_SIZE - 1 : 0]   crc_o         // output CRC of information Input
+          );
+          
+          logic [CRC_SIZE - 1 : 0] crc = 0;
+          logic [CRC_SIZE - 1 : 0] crc_next;
+          logic [CRC_SIZE - 1 : 0] crc_prev;
+          
+          
+          always_ff @( posedge clk_i )
+            if( !rst_n )
+              crc_o <= INIT[CRC_SIZE - 1 : 0];
+            else
+            begin
+               crc_o <= crc_prev;
+            end  
+
+          generate
+           always_comb
+             begin
+               crc_next = crc;
+               crc_prev = crc;
+               for( int i = 0; i < DATA_WIDTH; i ++ )
+                 begin
+                   crc_next[0] = crc_prev[CRC_SIZE - 1] ^ data_i[DATA_WIDTH - 1 - i];
+                   for( int j = 1; j < CRC_SIZE; j++ )
+                     if( POLY[j] )
+                       crc_next[j] = crc_prev[j - 1] ^ crc_prev[CRC_SIZE - 1] ^ data_i[DATA_WIDTH - 1 - i];
+                     else
+                       crc_next[j] = crc_prev[j - 1];
+                   crc_prev = crc_next;
+                 end
+               end
+          
+          endgenerate
+endmodule          
\ No newline at end of file