diff --git a/sim_1/imports/sim_1/tb_axi4_Lite_MM.v b/sim_1/imports/sim_1/tb_axi4_Lite_MM.v
index 0be83f1..e78ffea 100644
--- a/sim_1/imports/sim_1/tb_axi4_Lite_MM.v
+++ b/sim_1/imports/sim_1/tb_axi4_Lite_MM.v
@@ -96,18 +96,19 @@ module tb_axi4_Lite_MM;
            s_axi_wdata  = 32'h11_44_33_22;
            s_axi_wvalid = 1;
            s_axi_bready = 1;
-           #8
-           s_axi_awvalid = 0;               // added on 23022021.
-           s_axi_wvalid = 0;    
-           #8;
-           //s_axi_awaddr = 18'h04;
-           //s_axi_wdata  = 32'haa_bb_cc_ff;
-           #8;
-           s_axi_araddr = 18'h0C;       // read
-           s_axi_arvalid = 1;
-           s_axi_rready = 1;
+ //          #8
+//           s_axi_awvalid = 0;               // added on 23022021.
+//           s_axi_wvalid = 0;    
+//           #8;
+//           //s_axi_awaddr = 18'h04;
+//           //s_axi_wdata  = 32'haa_bb_cc_ff;
+//           #8;
+//           s_axi_araddr = 18'h0C;       // read
+//           s_axi_arvalid = 1;
+//           s_axi_rready = 1;
            
-           #8;
+ //          #4;
+            #24;
            s_axi_arvalid = 0;
 //           s_axi_araddr = 18'h04;
 //           s_axi_arvalid = 0;
@@ -122,26 +123,37 @@ module tb_axi4_Lite_MM;
 //           s_axi_awvalid = 0;               // added on 23022021.
 //           s_axi_wvalid = 0;  
           
-          #12
-          s_axi_araddr = 18'h10;  
-          #4 s_axi_arvalid = 1;         
-           s_axi_rready = 1;   
+//          #12
+//          s_axi_araddr = 18'h10;  
+//          #4 s_axi_arvalid = 1;         
+//           s_axi_rready = 1;   
           
-          #8;
+          #28;
            s_axi_arvalid = 0;           // write
            s_axi_awvalid = 1;
            s_axi_awaddr = 18'h1C;
            s_axi_wdata  = 32'h22_44_88_aa;  //66_55_77_88;
            s_axi_wvalid = 1;
            //s_axi_bready = 1;
+           
+           #28;
+           s_axi_araddr = 18'h0C;       // read
+            s_axi_arvalid = 1;
+            s_axi_rready = 1;
+           
+          #24;
+          s_axi_araddr = 18'h10;  
+            s_axi_arvalid = 1;         
+           s_axi_rready = 1;
                 
-           #12;
+//           #12;
+            #24;
            s_axi_araddr = 18'h1C;           // read
-           #4 s_axi_arvalid = 1;         
+           s_axi_arvalid = 1;         
            s_axi_rready = 1;   
            
-           #8;
-             s_axi_arvalid = 0;
+           //#8;
+            // s_axi_arvalid = 0;
             
 /*           repeat(8)
              begin
@@ -156,4 +168,9 @@ module tb_axi4_Lite_MM;
         end
 
         always #2 s_axi_aclk = ~s_axi_aclk;
+        always @(posedge s_axi_wready or posedge s_axi_awready)
+        begin
+        #8 s_axi_awvalid = 1'b0;
+           s_axi_wvalid  = 1'b0;
+        end
     endmodule
diff --git a/sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv b/sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv
index 229ae40..fe2e311 100644
--- a/sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv
+++ b/sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv
@@ -161,19 +161,26 @@
 	          // on the write address and data bus. This design 
 	          // expects no outstanding transactions.
 	          axi_awready <= 1'b1;
-	          
-	              /* if (!wadr_dne)                // adde for control of AWready.232022021.
+	          $display($time,"\t axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
+	               if (!wadr_dne)                // adde for control of AWready.232022021.
+	                 begin
 	                   axi_awready <= 1'b0;
+	                   $display($time,"\tIF Passed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
+	                 end
 	               else 
-	                   axi_awready <= 1'b1;*/
+	                 begin
+	                   axi_awready <= 1'b1;
+	                   $display($time,"\tIF Failed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
+	                 end
 	        end
 	      else           
 	        begin
-	      /*   if (!wadr_dne)                // adde for control of AWready.232022021.
-	               axi_awready <= 1'b0;
+	         if (wadr_dne)                // adde for control of AWready.232022021.
+	               axi_awready <= 1'b1;
 	          else 
-	               axi_awready <= 1'b1;*/
-	          axi_awready <= 1'b0;
+	               axi_awready <= 1'b0;
+//	          axi_awready <= 1'b0;
+	          $display($time,"\tELSE axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
 	        end
 	    end 
 	end