controlled _Wready

sim_1/imports/sim_1/tb_axi4_Lite_MM.v

@@ -134,6 +134,7 @@ module tb_axi4_Lite_MM;
            s_axi_awaddr = 18'h1C;
            s_axi_wdata  = 32'h22_44_88_aa;  //66_55_77_88;
            s_axi_wvalid = 1;
+           #8
            //s_axi_bready = 1;
            
            #28;
@@ -168,9 +169,17 @@ module tb_axi4_Lite_MM;
         end
 
         always #2 s_axi_aclk = ~s_axi_aclk;
-        always @(posedge s_axi_wready or posedge s_axi_awready)
-        begin
-        #8 s_axi_awvalid = 1'b0;
-           s_axi_wvalid  = 1'b0;
-        end
+//        always @(posedge s_axi_wready or posedge s_axi_awready)
+//        begin
+//        if (s_axi_wready ||s_axi_awready )
+//            begin
+//            #8 s_axi_awvalid = 1'b0;
+//               s_axi_wvalid  = 1'b0;
+//            end
+//        else
+//            begin
+//            #8 s_axi_awvalid = s_axi_awvalid;
+//               s_axi_wvalid  = s_axi_wvalid;
+//            end
+//        end
     endmodule

sources_1/imports/AXI4_liteMM/axi4_lite_v1_0_S_AXI_1.sv

@@ -161,26 +161,28 @@
 	          // on the write address and data bus. This design 
 	          // expects no outstanding transactions.
 	          axi_awready <= 1'b1;
-	          $display($time,"\t axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
+	        //  $display($time,"\t axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
 	               if (!wadr_dne)                // adde for control of AWready.232022021.
 	                 begin
-	                   axi_awready <= 1'b0;
-	                   $display($time,"\tIF Passed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
+	                   axi_awready <= 1'b0;  
+	                   
+	                   //$display($time,"\tIF Passed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
 	                 end
 	               else 
 	                 begin
-	                   axi_awready <= 1'b1;
-	                   $display($time,"\tIF Failed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
+	                   axi_awready <= 1'b1;  
+	                   //$display($time,"\tIF Failed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
 	                 end
 	        end
 	      else           
 	        begin
+	        axi_awready <= 1'b0;       // add on 24022021.
 	         if (wadr_dne)                // adde for control of AWready.232022021.
 	               axi_awready <= 1'b1;
 	          else 
 	               axi_awready <= 1'b0;
 //	          axi_awready <= 1'b0;
-	          $display($time,"\tELSE axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
+	          //$display($time,"\tELSE axi_awready = %d\t wadr_dne = %d",axi_awready,wadr_dne);
 	        end
 	    end 
 	end       
@@ -225,10 +227,25 @@
 	          // on the write address and data bus. This design 
 	          // expects no outstanding transactions. 
 	          axi_wready <= 1'b1;
+	           if (!wadr_dne)                // adde for control of AWready.242022021.
+	                 begin
+	                   axi_wready <= 1'b0;  
+	                   
+	                   //$display($time,"\tIF Passed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
+	                 end
+	               else 
+	                 begin
+	                   axi_wready <= 1'b1;  
+	                   //$display($time,"\tIF Failed axi_awready = %d \t wadr_dne = %d",axi_awready,wadr_dne);
+	                 end
 	        end
 	      else
 	        begin
 	          axi_wready <= 1'b0;
+	          if (wadr_dne)                // adde for control of AWready.242022021.
+	               axi_awready <= 1'b1;
+	          else 
+	               axi_awready <= 1'b0;
 	        end
 	    end 
 	end