new file: encoder_code_block_segmentation.srcs/sim_1/new/encoder_code_block_segmentation_tb.sv

new file:   encoder_code_block_segmentation.srcs/sources_1/new/encoder_code_block_segmentation_rtl.sv

encoder_code_block_segmentation.srcs/sim_1/new/encoder_code_block_segmentation_tb.sv

@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: BITSILICA PRIVATE LIMITED
+// Engineer: ABHIGNA.B
+// 
+// Create Date: 15/02/2021 10:47:19 AM
+// Design Name: ENCODER CODE BLOCK SEGMENTATION
+// Module Name: encoder_code_block_segmentation_tb
+// Project Name: POLAR ENCODER-DECODER
+// Target Devices: Zynq UltraScale+ ZCU111 Evaluation Platform (xczu28dr-ffvg1517-2-e)
+// Tool Versions: VIVADO 2020.1
+// Description: TB code to verify Code Block Segmentation block for Polar Encoder to break  
+// down larger messages into smaller blocks to encode.
+// 
+// Dependencies: 
+// 
+// Revision:2.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module encoder_code_block_segmentation_tb();
+
+
+
+parameter A=1600;         //length of input message
+parameter G=16385;        //length of rate matched output
+parameter Iseg=0;         //Sgmentation is enabled or not
+  
+ reg clock=1'b0;
+ reg reset_n='b1;
+ reg [A-1:0]a_in;
+ 
+ wire [A-1:0]c_out;
+ wire [((A-1)/2):0]c1_out,c2_out;
+ 
+ encoder_code_block_segmentation_rtl #(.A(A),.G(G),.Iseg(Iseg)) DUT(.clock(clock),.reset_n(reset_n),.a_in(a_in),.c_out(c_out),.c1_out(c1_out),.c2_out(c2_out));
+ 
+ always
+  begin
+   #2.03 clock = !clock;
+  end
+initial
+ begin
+ @(negedge clock);
+// #10;
+ reset_n=1'b0;
+  @(negedge clock);
+// #10;
+ reset_n=1'b1;
+//#10;
+a_in={{800{1'b1}},{800{1'b0}}};
+//a_in='haaaaa11111222223333344444555556666677777888889999900000111112222233333444445555566666777778888899999000001111122222333334444455555666667777788888999990000011111222223333344444555556666677777888889999900000111112222233333444445555566666777778888899999000001111122222333334444455555666667777788888999990000011111222223333344444555556666677777888889999900000111112222233333444445555566666777778888899999;
+//a_in='hFCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCD10ABDCDAFFFBDDCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCDFBEFCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCD10ABDCDAFFFBDDCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCDFBEFCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCD10ABDCDAFFFBDDCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCDFBEFCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCD10ABDCDAFFFBDDCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCDFBEFCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCD10ABDCDAFFFBDDCC457832CCCCDDDDDDDAAAAABCDBCDBCDCBDAAFCDFBE;
+repeat(5)
+ begin
+//#10;
+@(negedge clock);
+ a_in=$random;
+ end
+#100 $finish;
+end
+endmodule
+
+

encoder_code_block_segmentation.srcs/sources_1/new/encoder_code_block_segmentation_rtl.sv

@@ -0,0 +1,143 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: BITSILICA PRIVATE LIMITED
+// Engineer: ABHIGNA.B
+// 
+// Create Date: 15/02/2021 10:47:19 AM
+// Design Name: ENCODER CODE BLOCK SEGMENTATION
+// Module Name: encoder_code_block_segmentation_rtl
+// Project Name: POLAR ENCODER-DECODER
+// Target Devices: Zynq UltraScale+ ZCU111 Evaluation Platform (xczu28dr-ffvg1517-2-e)
+// Tool Versions: VIVADO 2020.1
+// Description: RTL code for Code Block Segmentation block for Polar Encoder to break  
+// down larger messages into smaller blocks to encode.
+// 
+// Dependencies: 
+// 
+// Revision:2.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module encoder_code_block_segmentation_rtl
+ #(
+  parameter A=1706,         //length of input message
+  parameter G=16385,        //length of rate matched output
+  parameter Iseg=1          //Segmentation is enabled or not
+   )
+  (
+   input wire clock,                              //system clock
+   input wire reset_n,                            //active low synchronous reset
+   input  wire [A-1:0]      a_in ,                //input message - A bit
+   output reg  [A-1:0]      c_out ,               //output message - A bit (when no segmentation is needed)
+   output reg  [((A-1)/2):0]  c1_out,c2_out       //output messages - ((A-1)/2) bits each(when segmentation is needed)
+   );
+   
+ // Checking A[0] == 1 then message length is ODD and en_even => 0
+ //          A[0] == 0 then message length is EVEN and en_even => 1 
+  wire en_even=(A[0])? 1'b0 : 1'b1; 
+  
+  parameter RESET     =2'b00;
+  parameter ISEG1_EVEN=2'b01;
+  parameter ISEG1_ODD =2'b10;
+  parameter ISEG0     =2'b11; 
+  
+  reg [1:0]state, next_state;
+ 
+///////////////present state logic////////////////// 
+always@(posedge clock)
+ begin
+  if(!reset_n)
+   state <= RESET;
+  else
+   state <= next_state;
+ end
+ 
+//////////////next state and output logic//////////////////////
+always@(*)
+begin
+
+  case(state)
+    RESET :                                           //reset state
+           begin
+            c1_out='d0;
+            c2_out='d0;
+            c_out ='d0;
+            case ({Iseg,en_even})
+                2'b00: next_state = ISEG0;
+                2'b01: next_state = ISEG0;
+                2'b10: next_state = ISEG1_ODD;
+                2'b11: next_state = ISEG1_EVEN;
+                default : next_state = RESET; 
+            endcase
+           end
+    ISEG1_EVEN:                                       //even message length
+                begin
+                c_out  = 'd0;
+                c1_out = a_in[((A/2)-1):0];
+                c2_out = a_in[A-1:(A/2)  ];
+                //next_state = ISEG1_EVEN;
+                end
+    ISEG1_ODD:                                        //odd message length
+                begin
+                c_out  = 'd0;
+                c1_out = a_in[((A)/2):0];
+                c2_out = {1'b0,a_in[A-1:((A/2)+1)]};
+                //next_state = ISEG1_ODD;
+                end
+    ISEG0:                                            //segmentation is not required.
+                begin
+                c_out  = a_in;
+                c1_out = 0;
+                c2_out = 0;
+                //next_state = ISEG0;
+                end
+  endcase
+ 
+    
+end  
+
+//////////////////////output logic////////////////////////
+/*always @(posedge clock)
+ begin
+ 
+  if(!reset_n)
+   begin
+   c1_out<='d0;
+   c2_out<='d0;
+   c_out <='d0;   
+   end
+   
+  else
+   begin
+   c1_out<='d0;
+   c2_out<='d0;
+   c_out <='d0;
+   case(state)
+    RESET :begin
+             c1_out<='d0;
+             c2_out<='d0;
+             c_out <='d0;
+           end
+    ISEG1_EVEN:begin
+                c_out  <= 'd0;
+                c1_out <= a_in[((A/2)-1):0];
+                c2_out <= a_in[A-1:(A/2)  ];
+               end
+    ISEG1_ODD:begin
+               c_out  <= 'd0;
+               c1_out <= a_in[((A)/2):0];
+               c2_out <= {1'b0,a_in[A-1:((A/2)+1)]};
+              end
+    ISEG0:begin
+            c_out  <= a_in;
+            c1_out <= 'd0;
+            c2_out <= 'd0;
+          end
+   endcase
+   end
+   
+ end*/
+endmodule
+