RISC_V/RISC_V/Cache/TLB_tb.v

module TLB_tb();
reg clock;
reg tlb_en;
reg clear_refer;
//reg [21:0] VPN;
reg [33:0] VA;
//wire [19:0] PPN_o;
wire [31:0] PA;
wire tlb_hit;

tlb uut(.clock(clock),.tlb_en(tlb_en),.clear_refer(clear_refer),.VA(VA),.PA(PA),.tlb_hit(tlb_hit));


initial begin
clock=1'b0;
tlb_en=1'b1;
clear_refer=1'b1;
//#3
//clear_refer=1'b0;
VA=34'b1000000000000000000110011010100101;
#50 
VA=34'b0101111000001010010101000111110001;
#50
VA=34'b1100000000000111100000000000011110;
#50 
VA=34'b0101001010001110100101001110100101;
#50 clear_refer =1'b0;
VA=34'b1010000001111000000000010111111001;

end


 always #10 clock = ~clock;
endmodule