From 12d298b6e0800053ab55b5315d5f5f35b38df2ec Mon Sep 17 00:00:00 2001 From: Naga Sitaram M Date: Wed, 11 Oct 2023 11:04:08 +0530 Subject: [PATCH] Initial Project version --- RISC_V/Pipeline/Alu.v | 580 +++++++++++++++++++++++++++ RISC_V/Pipeline/Control_Unit.v | 19 + RISC_V/Pipeline/Data_Memory.v | 21 + RISC_V/Pipeline/Decode_cycle.v | 126 ++++++ RISC_V/Pipeline/Execute_cycle.v | 109 +++++ RISC_V/Pipeline/Fetch_cycle.v | 82 ++++ RISC_V/Pipeline/Hazardunit.v | 92 +++++ RISC_V/Pipeline/Instruction_Memory.v | 22 + RISC_V/Pipeline/Load_Extension.v | 11 + RISC_V/Pipeline/Memory_cycle.v | 62 +++ RISC_V/Pipeline/PC_Adder.v | 8 + RISC_V/Pipeline/Pipeline.v | 157 ++++++++ RISC_V/Pipeline/Pipeline_tb.v | 179 +++++++++ RISC_V/Pipeline/Program_Counter.v | 19 + RISC_V/Pipeline/Register_File.v | 21 + RISC_V/Pipeline/Sign_Extension.v | 22 + RISC_V/Pipeline/Store_Extension.v | 9 + RISC_V/Pipeline/Writeback_cycle.v | 15 + RISC_V/Pipeline/mux2_1.v | 6 + RISC_V/Pipeline/mux3_1.v | 8 + 20 files changed, 1568 insertions(+) create mode 100644 RISC_V/Pipeline/Alu.v create mode 100644 RISC_V/Pipeline/Control_Unit.v create mode 100644 RISC_V/Pipeline/Data_Memory.v create mode 100644 RISC_V/Pipeline/Decode_cycle.v create mode 100644 RISC_V/Pipeline/Execute_cycle.v create mode 100644 RISC_V/Pipeline/Fetch_cycle.v create mode 100644 RISC_V/Pipeline/Hazardunit.v create mode 100644 RISC_V/Pipeline/Instruction_Memory.v create mode 100644 RISC_V/Pipeline/Load_Extension.v create mode 100644 RISC_V/Pipeline/Memory_cycle.v create mode 100644 RISC_V/Pipeline/PC_Adder.v create mode 100644 RISC_V/Pipeline/Pipeline.v create mode 100644 RISC_V/Pipeline/Pipeline_tb.v create mode 100644 RISC_V/Pipeline/Program_Counter.v create mode 100644 RISC_V/Pipeline/Register_File.v create mode 100644 RISC_V/Pipeline/Sign_Extension.v create mode 100644 RISC_V/Pipeline/Store_Extension.v create mode 100644 RISC_V/Pipeline/Writeback_cycle.v create mode 100644 RISC_V/Pipeline/mux2_1.v create mode 100644 RISC_V/Pipeline/mux3_1.v diff --git a/RISC_V/Pipeline/Alu.v b/RISC_V/Pipeline/Alu.v new file mode 100644 index 0000000..e196503 --- /dev/null +++ b/RISC_V/Pipeline/Alu.v @@ -0,0 +1,580 @@ +module Alu (Instruction, Imm_Extension_E, Aluout, a,b, ZeroE,PC, PCTarget_E); +//Declaration of Inputs +input [31:0] Instruction; +input signed [31:0] Imm_Extension_E; +input [ 31:0] a,b; +input signed [31:0] PC; +//Declarations of Outputs +output reg signed [31:0] Aluout; +output reg ZeroE; +output reg signed [31:0] PCTarget_E; +//Declaring wires +wire signed [31:0]A = a; +wire signed [31:0]B = b; +//Declaration of Parameters +// Instruction Types +parameter [7:0] r_to_r = 7'b0110011, + r_to_imm = 7'b0010011, + ld = 7'b0000011, + store = 7'b0100011, + upperimm = 7'b0110111, + branch = 7'b1100011; + //CSR = 7'b1110011; + +// REGISTER TO REGISTER TYPE +parameter [9:0] add = 10'b0000000_000, //Addition + sub = 10'b0100000_000, //Subtraction + slt = 10'b0000000_010, //Set if less than + sll = 10'b0000000_001, //Shift left logic + sltu = 10'b0000000_011, //Set if less than Unsigned + Xor = 10'b0000000_100, //Bitwise Xor + srl = 10'b0000000_101, //Shift right logic + sra = 10'b0100000_101, //Shift right arithmatic + Or = 10'b0000000_110, //Bitwise Or + And = 10'b0000000_111; //Bitwise And + +// REGISTER TO IMMEDIATE TYPE +parameter [2:0] addi = 3'b000, //Addition + slli = 3'b001, //Set if less than + slti = 3'b010, //Shift left logic + sltui = 3'b011, //Set if less than Unsigned + Xori = 3'b100, //Bitwise Xor + srli = 3'b101, //Shift right logic + //srai = 3'b101, //Shift right arithmatic + Ori = 3'b110, //Bitwise Or + andi = 3'b111; //Bitwise And + +// LOAD TYPE +parameter [2:0] LB = 3'b000, //Load Byte + LH = 3'b001, //Load Halfword + LW = 3'b010, //Load Word + LBU = 3'b100, //Load Byte Unsigned + LHU = 3'B101; //Load Halfword Unsigned + +// STORE TYPE +parameter [2:0] SB = 3'b000, // STORE BYTE + SH = 3'b001, // STORE HALF WORD + SW = 3'b010; // STORE WORD + +// UPPER IMMEDIATE TYPE +parameter [6:0] LUI = 7'b0110111, // LOAD UPPER IMMEDIATE + AUIPC = 7'b0010111; //ADD UPPER IMMEDIATE + +// BRANCH TYPE +parameter [2:0] BEQ = 3'b000, // BRANCH EQUAL + BNE = 3'b001, // BRANCH NOT EQUAL + BLT = 3'b100, // BRANCH LESS THAN + BGE = 3'b101, // BRANCH GREATER THAN + BLTU = 3'b110, // BRANCH LESS THAN UNSINGNED + BGEU = 3'b111; // BRANCH GREATER THAN UNSINGED + +// JUMP TYPE +parameter [6:0] JAL = 7'b1101111, //JUMP AND LINK + JALR = 7'b1100111; //JUMP AND LINK REGISTER +/* +// CSR Type +parameter [2:0] CSRRW = 3'b001, + CSRRS = 3'b010, + CSRRC = 3'b011, + CSRRWI = 3'b101, + CSRRSI = 3'b110, + CSRRCI = 3'b111; + */ +always@(*) + begin + case(Instruction [6:0] ) + r_to_r : //Register to Register + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + Aluout = 32'b0; + case({Instruction [31:25] ,Instruction[14:12]}) //Funct7,Funct3 Values + add : Aluout = A + B; + sub : Aluout = A - B; + sll : Aluout = A << B[4:0]; + slt : begin + if(A < B) + Aluout = 1; + else + Aluout = 0; + end + sltu: begin + if(a < b) + Aluout = 1; + else + Aluout = 0; + end + Xor : Aluout = A ^ B; + srl : Aluout = A >> B[4:0]; + sra : Aluout = A >>> B[4:0]; + Or : Aluout = A || B; + And : Aluout = A && B; + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + endcase + end + + r_to_imm: + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + Aluout = 32'b0; + case(Instruction[14:12] ) //Funct3 values + addi : Aluout = A + B; + slli : Aluout = A << b; + slti : begin + if(A < B) + Aluout = 1; + else + Aluout = 0; + end + sltui: begin + if(a < b) + Aluout = 1; + else + Aluout = 0; + end + Xori : Aluout = A ^ B; + srli : begin + if(B[10] == 1) + Aluout = A >>> b; + else + Aluout = A >> b; + end + Ori : Aluout = A | B; + andi : Aluout = A & B; + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + endcase + end + ld: + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + Aluout = A + B; + end + store: + begin + Aluout = A + B; + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + branch: + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + Aluout = 32'b0; + case(Instruction [14:12]) + BEQ : begin + if(A == B) + begin + ZeroE = 1'b1; + PCTarget_E = PC + Imm_Extension_E; + end + else + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + end + BNE : begin + if(A != B) + begin + ZeroE = 1'b1; + PCTarget_E = PC + Imm_Extension_E; + end + else + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + end + BLT : begin + if(A < B) + begin + ZeroE = 1'b1; + PCTarget_E = PC + Imm_Extension_E; + end + else + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + end + BGE : begin + if(A >= B) + begin + ZeroE = 1'b1; + PCTarget_E = PC + Imm_Extension_E; + end + else + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + end + BLTU : begin + if(a < b) + begin + ZeroE = 1'b1; + PCTarget_E = PC + Imm_Extension_E; + end + else + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + end + BGEU : begin + if(a >= b) + begin + ZeroE = 1'b1; + PCTarget_E = PC + Imm_Extension_E; + end + else + begin + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + end + default : begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + endcase + end + LUI: + begin + Aluout = B; + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + AUIPC: + begin + Aluout = PC+B; + ZeroE = 1'b0; + PCTarget_E = 32'b0; + end + JAL: + begin + Aluout = PC+32'h00000004; + PCTarget_E = PC+B; + ZeroE = 1'b0; + end + JALR: + begin + Aluout = PC+32'h00000004; + PCTarget_E = ((PC+B)&32'hFFFFFFFE); + ZeroE = 1'b0; + end +/* CSR: + begin + case(Instruction [14:12]) + CSRRW || CSRRS || CSRRC || CSRRWI || CSRRSI || CSRRCI: + begin + Aluout <= {{20{1'b0}},Instruction [20:31]}; + PCTarget_E <= PCTarget_E; + end + endcase + end +*/ + default : begin + Aluout = 32'b0; + PCTarget_E = 32'b0; + ZeroE = 1'b0; + end + endcase + end +endmodule +/* +module Alu (Instruction, Imm_Extension_E, Aluout, A,B, ZeroE,PC, PCTarget_E); +input [31:0] Instruction; +input signed [31:0] Imm_Extension_E; +input signed [31:0] A,B; +input signed [31:0] PC; +output reg [31:0] Aluout; +output reg ZeroE; +output reg [31:0] PCTarget_E; + +parameter [7:0] r_to_r = 7'b0110011, + r_to_imm = 7'b0010011, + ld = 7'b0000011, + store = 7'b0100011, + branch = 7'b1100011; + +// REGISTER TO REGISTER TYPE +parameter [9:0] add = 10'b0000000_000, + sub = 10'b0100000_000, + slt = 10'b0000000_010, + sll = 10'b0000000_001, + sltu= 10'b0000000_011, + Xor = 10'b0000000_100, + srl = 10'b0000000_101, + sra = 10'b0100000_101, + Or = 10'b0000000_110, + And = 10'b0000000_111; + +// REGISTER TO IMMEDIATE TYPE +parameter [2:0] addi = 3'b000, + slli = 3'b001, + slti = 3'b010, + sltui= 3'b011, + Xori = 3'b100, + srli = 3'b101, + //srai = 3'b101, + Ori = 3'b110, + andi = 3'b111; + +//LOAD TYPE +parameter [2:0] LB = 3'b000, + LH = 3'b001, + LW = 3'b010, + LBU= 3'b100, + LHU= 3'B101; + +//STORE TYPE + +parameter [2:0] SB = 3'b000, // STORE BYTE + SH = 3'b001, // STORE HALF WORD + SW = 3'b010; // STORE WORD + +// UPPER IMMEDIATE TYPE +parameter [6:0] LUI = 7'b0110111, // LOAD UPPER IMMEDIATE + AUIPC =7'b0010111; //ADD UPPER IMMEDIATE +// BRANCH TYPE +parameter [2:0] BEQ = 3'b000, // BRANCH EQUAL + BNE = 3'b001, // BRANCH NOT EQUAL + BLT = 3'b100, // BRANCH LESS THAN + BGE = 3'b101, // BRANCH GREATER THAN + BLTU= 3'b110, // BRANCH LESS THAN UNSINGNED + BGEU= 3'b111; // BRANCH GREATER THAN UNSINGED +//JUMP TYPE +parameter [6:0] JAL = 7'b1101111, + JALR = 7'b1100111; + +always@(*) +begin + case(Instruction [6:0] ) + r_to_r : + begin + //ZeroE = 0; + //PCTarget_E = PCTarget_E; + case({Instruction [31:25] ,Instruction[14:12]}) + + add : Aluout = A + B; + sub : Aluout = A - B; + sll : Aluout = A << B[4:0]; + slt : + begin + if( A < B) + Aluout <= 1; + else + Aluout <= 0; + end + sltu: + begin + if($unsigned(A) < $unsigned(B)) + Aluout = 1; + else + Aluout = 0; + end + Xor : Aluout = A ^ B; + srl : Aluout = A >> B[4:0]; + sra : Aluout = A >>> B[4:0]; + Or : Aluout = A || B; + And : Aluout = A && B; + + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = PCTarget_E; + end + endcase + end + + r_to_imm: + begin + //ZeroE = 0; + //PCTarget_E = PCTarget_E; + case(Instruction[14:12] ) + addi : Aluout = A + B; + slli : Aluout = A << B; + slti : + begin + if(A < B) + Aluout = 1; + else + Aluout = 0; + end + sltui: + begin + if($unsigned(A) < $unsigned(B)) + Aluout = 1; + else + Aluout = 0; + end + Xori : Aluout = A ^ B; + srli : + begin + if(B[10] == 0) + Aluout = A >> B; + end + srai : + begin + if(B[10] == 1) + Aluout = A >>> B; + end + Ori : Aluout = A | B; + andi : Aluout = A & B; + + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = PCTarget_E; + end + endcase + end + + ld: + begin + //ZeroE = 0; + //PCTarget_E = PCTarget_E; + case(Instruction [14:12]) + LB : Aluout = A + B; + LH : Aluout = A + B; + LW : Aluout = A + B; + LBU : Aluout = $unsigned(A) + $unsigned(B); + LHU : Aluout = $unsigned(A) + $unsigned(B); + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = PCTarget_E; + end + endcase + end + + store: + begin + //ZeroE = 1'b0; + //PCTarget_E = PCTarget_E; + case(Instruction [14:12]) + SB : Aluout = A +B; + SH : Aluout = A + B; + SW : Aluout = A + B; + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = PCTarget_E; + end + endcase + end + + branch: + begin + //Aluout = 32'b0; + case(Instruction [14:12]) + BEQ : + begin + + if(A == B)begin + ZeroE = 1; + PCTarget_E = PC + Imm_Extension_E;end + else begin + ZeroE = 0; + PCTarget_E = PCTarget_E; end + end + BNE : + begin + if(A != B)begin + ZeroE = 1; + PCTarget_E = PC + Imm_Extension_E ;end + + else begin + ZeroE = 0; + PCTarget_E = PCTarget_E; end + end + BLT : + begin + if(A < B)begin + ZeroE = 1; + PCTarget_E = PC + Imm_Extension_E; end + + else begin + ZeroE = 0; + PCTarget_E = PCTarget_E; end + + end + BGE : + begin + if(A >= B)begin + ZeroE = 1; + PCTarget_E = PC + Imm_Extension_E;end + + else begin + ZeroE = 0; + PCTarget_E = PCTarget_E; end + + end + BLTU : + begin + if($unsigned(A) < $unsigned(B))begin + ZeroE = 1; + PCTarget_E = PC + Imm_Extension_E; + end + else begin + ZeroE = 0; + PCTarget_E = PCTarget_E; end + + end + BGEU : + begin + if($unsigned(A) >= $unsigned(B)) + begin + ZeroE = 1; + PCTarget_E = PC + Imm_Extension_E; + end + else begin + ZeroE = 0; + PCTarget_E = PCTarget_E; end + + end + default :begin + Aluout = 32'b0; + ZeroE = 1'b0; + PCTarget_E = PCTarget_E; + end + endcase + end + LUI: + begin + Aluout = B; + end + AUIPC: + begin + Aluout = PC+B; + end + JAL: + begin + Aluout = PC+32'h00000004; + PCTarget_E = PC+B; + end + JALR: + begin + Aluout = PC+32'h00000004; + PCTarget_E = ((PC+B)&32'hFFFFFFFE); + end + default:begin + ZeroE = ZeroE; + PCTarget_E = PCTarget_E; + end + endcase +end +endmodule +*/ \ No newline at end of file diff --git a/RISC_V/Pipeline/Control_Unit.v b/RISC_V/Pipeline/Control_Unit.v new file mode 100644 index 0000000..1ef8865 --- /dev/null +++ b/RISC_V/Pipeline/Control_Unit.v @@ -0,0 +1,19 @@ +module Control_Unit(Opcode,RegWrite,MemWrite,Result_Select,Branch,Jump,Rs2_Select); +//Declaring Inputs and Outputs + input [6:0]Opcode; + output RegWrite,MemWrite,Result_Select,Branch,Jump,Rs2_Select; + + + assign RegWrite = (Opcode == 7'b0000011 || Opcode == 7'b0110011 || Opcode == 7'b0010011 || Opcode == 7'b0110111 || Opcode == 7'b0010111 || Opcode == 7'b1101111 || Opcode == 7'b1100111) ? 1'b1 : + 1'b0 ; + assign MemWrite = (Opcode == 7'b0100011) ? 1'b1 : + 1'b0 ; + assign Result_Select = (Opcode == 7'b0000011) ? 1'b1 : + 1'b0 ; + assign Branch = (Opcode == 7'b1100011) ? 1'b1 : + 1'b0 ; + assign Jump = (Opcode == 7'b1101111 || Opcode == 7'b1100111)? 1'b1 : 1'b0; + + assign Rs2_Select = (Opcode == 7'b0010011 || Opcode == 7'b0000011 || Opcode == 7'b0100011 || Opcode == 7'b0110111 | + Opcode == 7'b0010111 || Opcode == 7'b1101111 || Opcode == 7'b1100111)? 1'b1 : 1'b0 ; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Data_Memory.v b/RISC_V/Pipeline/Data_Memory.v new file mode 100644 index 0000000..3ad7b6d --- /dev/null +++ b/RISC_V/Pipeline/Data_Memory.v @@ -0,0 +1,21 @@ +module Data_Memory(clk,rst,WE,WD,A,RD); + + input clk,rst,WE; + input [31:0]A,WD; + output [31:0]RD; + + reg [31:0] mem [1023:0]; + + always @ (posedge clk) + begin + if(WE) + mem[A] <= WD; + end + + assign RD = (rst==1) ? 32'd0 : mem[A]; + + initial begin + mem[0] = 32'h00000000; + end + +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Decode_cycle.v b/RISC_V/Pipeline/Decode_cycle.v new file mode 100644 index 0000000..63ad19f --- /dev/null +++ b/RISC_V/Pipeline/Decode_cycle.v @@ -0,0 +1,126 @@ +module Decode_cycle(clk, rst, clear, RegWrite_W, RD_W, Instruction_D, PC_D, Result_W, RegWrite_E, MemWrite_E, +Result_Select_E, Branch_E, Jump_E, Rs2_Select_E, RD1_E, RD2_E, Imm_Extension_E, RS1_E, RS2_E, RD_E, PC_E, Instruction_E); + + // Declaring Inputs and Outputs + input clk, rst, clear, RegWrite_W; + input [4:0] RD_W; + input [31:0] Instruction_D, PC_D, Result_W; + + output RegWrite_E, MemWrite_E, Result_Select_E, Branch_E, Jump_E, Rs2_Select_E; + output signed [31:0] RD1_E, RD2_E, Imm_Extension_E; + output [4:0] RS1_E, RS2_E, RD_E; + output [31:0] PC_E,Instruction_E; + + // Declare Interim Wires + wire RegWrite_D, MemWrite_D, Result_Select_D, Branch_D, Jump_D, Rs2_Select_D; + wire signed [31:0] RD1_D, RD2_D, Imm_Extension_D; + wire [31:0] Instruction_D; + + // Declaration of Interim Register + reg RegWrite_D_reg, MemWrite_D_reg, Result_Select_D_reg, Branch_D_reg, Jump_D_reg, Rs2_Select_D_reg; + reg [31:0] RD1_D_reg, RD2_D_reg, Imm_Extension_D_reg; + reg [4:0] RS1_D_reg, RS2_D_reg, RD_D_reg; + reg [31:0] PC_D_reg, Instruction_D_reg; + + + // Initiate the modules + // Control Unit + Control_Unit Control_Unit(.Opcode(Instruction_D[6:0]), + .RegWrite(RegWrite_D), + .MemWrite(MemWrite_D), + .Result_Select(Result_Select_D), + .Branch(Branch_D), + .Jump(Jump_D), + .Rs2_Select(Rs2_Select_D) + ); + + // Register File + Register_File Registers(.clk(clk), + .rst(rst), + .WE3(RegWrite_W), + .WD3(Result_W), + .A1(Instruction_D[19:15]), + .A2(Instruction_D[24:20]), + .A3(RD_W), + .RD1(RD1_D), + .RD2(RD2_D) + ); + + // Sign Extension + Sign_Extension Extension ( + .Instruction(Instruction_D[31:0]), + .Imm(Imm_Extension_D) + ); + + // Declaring Register Logic + always @(posedge clk or posedge rst) + begin + if(rst == 1'b1) + begin + RegWrite_D_reg <= 1'b0; + MemWrite_D_reg <= 1'b0; + Result_Select_D_reg <= 1'b0; + Branch_D_reg <= 1'b0; + Jump_D_reg <= 1'b0; + Rs2_Select_D_reg <= 1'b0; + RD1_D_reg <= 32'h00000000; + RD2_D_reg <= 32'h00000000; + Imm_Extension_D_reg <= 32'h00000000; + RD_D_reg <= 5'h00; + PC_D_reg <= 32'h00000000; + RS1_D_reg <= 5'h00; + RS2_D_reg <= 5'h00; + Instruction_D_reg <= 32'h00000000; + end + else if(clear) //NOP + begin + RegWrite_D_reg <= 1'b0; + MemWrite_D_reg <= 1'b0; + Result_Select_D_reg <= 1'b0; + Branch_D_reg <= 1'b0; + Jump_D_reg <= 1'b0; + Rs2_Select_D_reg <= 1'b0; + RD1_D_reg <= 32'h00000000; + RD2_D_reg <= 32'h00000000; + Imm_Extension_D_reg <= 32'h00000000; + RD_D_reg <= 5'h00; + PC_D_reg <= 32'hxxxxxxxx; + RS1_D_reg <= 5'h00; + RS2_D_reg <= 5'h00; + Instruction_D_reg <= 32'h00000033; + end + else + begin + RegWrite_D_reg <= RegWrite_D; + MemWrite_D_reg <= MemWrite_D; + Result_Select_D_reg <= Result_Select_D; + Branch_D_reg <= Branch_D; + Jump_D_reg <= Jump_D; + Rs2_Select_D_reg <= Rs2_Select_D; + RD1_D_reg <= RD1_D; + RD2_D_reg <= RD2_D; + Imm_Extension_D_reg <= Imm_Extension_D; + RD_D_reg <= Instruction_D[11:7]; + PC_D_reg <= PC_D; + RS1_D_reg <= Instruction_D[19:15]; + RS2_D_reg <= Instruction_D[24:20]; + Instruction_D_reg <= Instruction_D; + end + end + + // Output asssign statements + assign RegWrite_E = RegWrite_D_reg; + assign MemWrite_E = MemWrite_D_reg; + assign Result_Select_E = Result_Select_D_reg; + assign Branch_E = Branch_D_reg; + assign Jump_E = Jump_D_reg; + assign Rs2_Select_E = Rs2_Select_D_reg; + assign RD1_E = RD1_D_reg; + assign RD2_E = RD2_D_reg; + assign Imm_Extension_E = Imm_Extension_D_reg; + assign RD_E = RD_D_reg; + assign PC_E = PC_D_reg; + assign RS1_E = RS1_D_reg; + assign RS2_E = RS2_D_reg; + assign Instruction_E = Instruction_D_reg; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Execute_cycle.v b/RISC_V/Pipeline/Execute_cycle.v new file mode 100644 index 0000000..62cfe51 --- /dev/null +++ b/RISC_V/Pipeline/Execute_cycle.v @@ -0,0 +1,109 @@ +module Execute_cycle(clk, rst, RegWrite_E, MemWrite_E, Result_Select_E, Branch_E, Jump_E, Rs2_Select_E, +RD1_E, RD2_E, Imm_Extension_E, Instruction_E, RD_E, PC_E, Result_W, ForwardA_E, ForwardB_E, PC_Select_E, +RegWrite_M, MemWrite_M, Result_Select_M, RD_M, WriteData_M, Alu_Result_M, PCTarget_E, Operation_M); + + // Declaration of Inputs and Outputs + input clk, rst, RegWrite_E,MemWrite_E,Result_Select_E,Branch_E,Jump_E,Rs2_Select_E; + input [31:0] RD1_E, RD2_E, Imm_Extension_E; + input [31:0] Instruction_E; + input [4:0] RD_E; + input [31:0] PC_E; + input [31:0] Result_W; + input [1:0] ForwardA_E, ForwardB_E; + + output PC_Select_E, RegWrite_M, MemWrite_M, Result_Select_M; + output [4:0] RD_M; + output [31:0] WriteData_M; + output [31:0] Alu_Result_M; + output [31:0] PCTarget_E; + output [2:0] Operation_M; + + // Declaration of Interim Wires + wire [31:0] A, B_temp; + wire [31:0] B; + wire [31:0] Alu_Result_E; + wire ZeroE; + wire [31:0] Store_extension; + + // Declaration of Register + reg RegWrite_E_reg, MemWrite_E_reg, Result_Select_E_reg; + reg [4:0] RD_E_reg; + reg [31:0] WriteData_E_reg; + reg [31:0] Alu_Result_E_reg; + reg [2:0] Operation_E_reg; + + // Declaration of Modules + // 3 by 1 Mux for A + mux3_1 mux_A(.a(RD1_E), + .b(Alu_Result_M), + .c(Result_W), + .s(ForwardA_E), + .y(A) + ); + + // 3 by 1 Mux for B_temp + mux3_1 mux_B_temp(.a(RD2_E), + .b(Alu_Result_M), + .c(Result_W), + .s(ForwardB_E), + .y(B_temp) + ); + // Mux for B + mux2_1 mux_B(.a(B_temp), + .b(Imm_Extension_E), + .s(Rs2_Select_E), + .y(B) + ); + + // ALU Unit + Alu alu(.Instruction(Instruction_E), + .Imm_Extension_E(Imm_Extension_E), + .Aluout(Alu_Result_E), + .a(A), + .b(B), + .ZeroE(ZeroE), + .PC(PC_E), + .PCTarget_E(PCTarget_E) + ); + + Store_Extension Store(.WriteData_E_temp(B_temp), + .Operation(Instruction_E[14:12]), + .WriteData_E(Store_extension) + ); + + // Register Logic + always @(posedge clk or posedge rst) + begin + if(rst == 1'b1) + begin + RegWrite_E_reg <= 1'b0; + MemWrite_E_reg <= 1'b0; + Result_Select_E_reg <= 1'b0; + RD_E_reg <= 5'h00; + WriteData_E_reg <= 32'h00000000; + Alu_Result_E_reg <= 32'h00000000; + Operation_E_reg <= 3'b000; + end + else + begin + RegWrite_E_reg <= RegWrite_E; + MemWrite_E_reg <= MemWrite_E; + Result_Select_E_reg <= Result_Select_E; + RD_E_reg <= RD_E; + WriteData_E_reg <= Store_extension; + Alu_Result_E_reg <= Alu_Result_E; + Operation_E_reg <= Instruction_E[14:12]; + end + end + + // Output Assignments + assign PC_Select_E = Jump_E|(ZeroE & Branch_E); + assign RegWrite_M = RegWrite_E_reg; + assign MemWrite_M = MemWrite_E_reg; + assign Result_Select_M = Result_Select_E_reg; + assign RD_M = RD_E_reg; + assign WriteData_M = WriteData_E_reg; + assign Alu_Result_M = Alu_Result_E_reg; + assign Operation_M = Operation_E_reg; + +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Fetch_cycle.v b/RISC_V/Pipeline/Fetch_cycle.v new file mode 100644 index 0000000..1353a5d --- /dev/null +++ b/RISC_V/Pipeline/Fetch_cycle.v @@ -0,0 +1,82 @@ +//IF_ID_Stage +module Fetch_cycle(enable,clk, rst, enable, clear_d, PC_Select_E, PCTarget_E, Instruction_D, PC_D); + // Declare input & outputs +// input [31:0]instruction_fetch; + // input Instruction_enable; + input clk, rst; + input enable, clear_d; + input PC_Select_E; + input [31:0] PCTarget_E; + output [31:0] Instruction_D; + output [31:0] PC_D; + + // Declaring interim wires + wire [31:0] PC_F, PCF, PCPlus4F; + wire [31:0] Instruction_F; + wire [31:0] PC_F_reg_temp = 0, Instruction_F_reg_temp = 0; + + // Declaration of Register + reg [31:0] Instruction_F_reg; + reg [31:0] PC_F_reg; + + + // Initiation of Modules + // Declare PC Mux + mux2_1 PC_MUX (.a(PCPlus4F), + .b(PCTarget_E), + .s(PC_Select_E), + .y(PCF) + ); + + // Declare PC Counter + Program_Counter Program_Counter (.clk(clk), + .rst(rst), + .enable(enable), + .PC(PC_F), + .PC_Next(PCF) + ); + + // Declare Instruction Memory + Instruction_Memory IMem(//.clk(clk), + .rst(rst), + // .Instruction_enable(Instruction_enable), +// .instruction_fetch(instruction_fetch), + .A(PC_F), + .RD(Instruction_F) + ); + + // Declare PC adder + PC_Adder PC_adder(.a(PC_F), + .b(32'h00000004), + .y(PCPlus4F) + ); + + // Fetch Cycle Register Logic + always @(posedge clk or posedge rst) + begin + if(rst == 1'b1) + begin + Instruction_F_reg <= 32'h00000000; + PC_F_reg <= 32'h00000000; + end + else if(clear_d) //Control Hazard + begin + Instruction_F_reg <= 32'b0000000_00000_00000_000_00000_0110011; // dummy innstruction + PC_F_reg <= 10'bxxxxxxxxxx; // dummy instrction indicated by x - ( nop) + end + else if(enable) + begin + PC_F_reg <=PC_F_reg_temp; // loop back + Instruction_F_reg <= Instruction_F_reg_temp; // loop back + end + else + begin + Instruction_F_reg <= Instruction_F; + PC_F_reg <= PC_F; + end + end + + // Assigning Registers Value to the Output port + assign Instruction_D = Instruction_F_reg; + assign PC_D = PC_F_reg; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Hazardunit.v b/RISC_V/Pipeline/Hazardunit.v new file mode 100644 index 0000000..523a59d --- /dev/null +++ b/RISC_V/Pipeline/Hazardunit.v @@ -0,0 +1,92 @@ +module Hazardunit(enable, clear, clear_d , ForwardA_E, ForwardB_E,opcode_D,opcode_E, RS1_D, RS2_D, RD_E, +RS1_E,RS2_E, RD_M, RD_W, RegWrite_M, RegWrite_W, Result_Select_E, PC_Select_E); + + input [6:0] opcode_D,opcode_E; + input [4:0] RS1_E, RS2_E,RD_E, RD_M,RD_W, RS1_D,RS2_D; + input RegWrite_M, RegWrite_W,Result_Select_E, PC_Select_E; + output reg enable, clear,clear_d; + output reg [1:0] ForwardA_E, ForwardB_E; + parameter [6:0]r_to_r = 7'b0110011, + r_to_imm = 7'b0010011, + ld = 7'b0000011, + store = 7'b010001, + branch = 7'b1100011, + lui = 7'b0110111, + auipc = 7'b0010111, + jal = 7'b1101111, + jalr = 7'b1100111; + + + always @(*) + begin + // control hazard used for fulsing the ooperation + if(PC_Select_E) + begin + clear <= 1'b1; + clear_d <= 1'b1;//control hazard + enable <=1'b0; + ForwardA_E <= 2'b00; + ForwardB_E <= 2'b00; + end +//DATA HAZARD WHEN THERE IS A LOAD TYPE INSTRUCTION + + else if( ( RS1_D == RD_E && opcode_D !=lui && opcode_D != auipc && opcode_D != jal) && Result_Select_E == 1'b1) + begin + enable <= 1'b1; + clear <= 1'b1; + clear_d <= 1'b0; + ForwardA_E <= 2'b00; + ForwardB_E <= 2'b00; + end + +else if( ((RS2_D == RD_E )&& (opcode_D == store || opcode_D == branch || opcode_D == r_to_r)) && Result_Select_E == 1'b1) + begin + enable <= 1'b1; + clear <= 1'b1; + clear_d <= 1'b0; + ForwardA_E <= 2'b00; + ForwardB_E <= 2'b00; + end + + else if( ( (RS1_E == RD_M) && RegWrite_M) && opcode_E !=lui && opcode_E != auipc && opcode_E != jal ) + begin + enable <= 1'b0; + ForwardA_E <= 2'b01; + ForwardB_E <= 2'b00; + clear <= 1'b0; + clear_d <= 1'b0; + end + else if( ( (RS1_E == RD_W) && RegWrite_W) && opcode_E !=lui && opcode_E != auipc && opcode_E != jal) + begin + enable <= 1'b0; + ForwardA_E <= 2'b10; + ForwardB_E <= 2'b00; + clear <= 1'b0; + clear_d <= 1'b0; + end + else if(( (RS2_E == RD_M) && RegWrite_M) && (opcode_E == store || opcode_E == branch || opcode_E == r_to_r)) + begin + enable <= 1'b0; + ForwardA_E <= 2'b00; + ForwardB_E <= 2'b01; + clear <= 1'b0; + clear_d <= 1'b0; + end + else if (( (RS2_E == RD_W) && RegWrite_W) && (opcode_E == store || opcode_E == branch || opcode_E == r_to_r)) + begin + enable <= 1'b0; + ForwardA_E <= 2'b00; + ForwardB_E <= 2'b10; + clear <= 1'b0; + clear_d <= 1'b0; + end + else + begin + enable <= 1'b0; + ForwardA_E <= 2'b00; + ForwardB_E <= 2'b00; + clear <= 1'b0; + clear_d <= 1'b0; + end + end +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Instruction_Memory.v b/RISC_V/Pipeline/Instruction_Memory.v new file mode 100644 index 0000000..ae39253 --- /dev/null +++ b/RISC_V/Pipeline/Instruction_Memory.v @@ -0,0 +1,22 @@ +module Instruction_Memory(rst,A,RD); + input rst;//clk; + input [31:0]A; + output [31:0]RD; + //input Instruction_enable; + //input [31:0] instruction_fetch; + +//Memory Creation + reg [31:0] Mem [1023:0]; + //reg [31:0] Mem [2^32:0]; + /* + always@(posedge clk) + begin + if(Instruction_enable) + begin + Mem[A] <= instruction_fetch; + end + end + */ + assign RD = (rst == 1'b1) ? 32'b0 : Mem[A]; + +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Load_Extension.v b/RISC_V/Pipeline/Load_Extension.v new file mode 100644 index 0000000..757b471 --- /dev/null +++ b/RISC_V/Pipeline/Load_Extension.v @@ -0,0 +1,11 @@ +module Load_Extension(ReadData_M_temp,Operation,ReadData_M); +input [31:0] ReadData_M_temp; +input [2:0]Operation; +output [31:0] ReadData_M; + +assign ReadData_M = (Operation == 3'b000)?{{24{ReadData_M_temp[7]}},ReadData_M_temp[7:0]} : + (Operation == 3'b001)?{{16{ReadData_M_temp[15]}},ReadData_M_temp[15:0]} : + (Operation == 3'b010)? ReadData_M_temp : + (Operation == 3'b100)?{{24'b0},ReadData_M_temp[7:0]} : + (Operation == 3'b101)?{{16'b0},ReadData_M_temp[15:0]} : 32'hxxxxxxxx; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Memory_cycle.v b/RISC_V/Pipeline/Memory_cycle.v new file mode 100644 index 0000000..9ca29f9 --- /dev/null +++ b/RISC_V/Pipeline/Memory_cycle.v @@ -0,0 +1,62 @@ +module Memory_cycle(clk, rst, RegWrite_M, MemWrite_M, Result_Select_M, RD_M, WriteData_M, + Alu_Result_M, Operation_M, RegWrite_W, Result_Select_W, RD_W, Alu_Result_W, ReadData_W); + + // Declaration of I/Os + input clk, rst, RegWrite_M, MemWrite_M, Result_Select_M; + input [4:0] RD_M; + input [31:0] WriteData_M, Alu_Result_M; + input [2:0] Operation_M; + + output RegWrite_W, Result_Select_W; + output [4:0] RD_W; + output [31:0] Alu_Result_W, ReadData_W; + + // Declaration of Intermediate Wires + wire [31:0] ReadData_M,ReadData_M_temp ; + + // Declaration of Intermediate Registers + reg RegWrite_M_reg, Result_Select_M_reg; + reg [4:0] RD_M_reg; + reg [31:0] Alu_Result_M_reg, ReadData_M_reg; + + // Declaration of Module Initiation + Data_Memory Data_Memory(.clk(clk), + .rst(rst), + .WE(MemWrite_M), + .WD(WriteData_M), + .A(Alu_Result_M), + .RD(ReadData_M_temp) + ); + Load_Extension Load(.ReadData_M_temp(ReadData_M_temp), + .Operation(Operation_M), + .ReadData_M(ReadData_M) + ); + // Memory Stage Register Logic + always @(posedge clk or posedge rst) + begin + if (rst == 1'b1) + begin + RegWrite_M_reg <= 1'b0; + Result_Select_M_reg <= 1'b0; + RD_M_reg <= 5'b00000; + Alu_Result_M_reg <= 32'h00000000; + ReadData_M_reg <= 32'h00000000; + end + else + begin + RegWrite_M_reg <= RegWrite_M; + Result_Select_M_reg <= Result_Select_M; + RD_M_reg <= RD_M; + Alu_Result_M_reg <= Alu_Result_M; + ReadData_M_reg <= ReadData_M; + end + end + + // Declaration of output assignments + assign RegWrite_W = RegWrite_M_reg; + assign Result_Select_W = Result_Select_M_reg; + assign RD_W = RD_M_reg; + assign Alu_Result_W = Alu_Result_M_reg; + assign ReadData_W = ReadData_M_reg; + +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/PC_Adder.v b/RISC_V/Pipeline/PC_Adder.v new file mode 100644 index 0000000..6749690 --- /dev/null +++ b/RISC_V/Pipeline/PC_Adder.v @@ -0,0 +1,8 @@ +module PC_Adder (a,b,y); + + input [31:0]a,b; + output [31:0]y; + + assign y = a + b; + +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Pipeline.v b/RISC_V/Pipeline/Pipeline.v new file mode 100644 index 0000000..3466f75 --- /dev/null +++ b/RISC_V/Pipeline/Pipeline.v @@ -0,0 +1,157 @@ +/* +`include "Fetch_cycle.v" +`include "Decode_cycle.v" +`include "Execute_cycle.v" +`include "Memory_cycle.v" +`include "Writeback_cycle.v" +`include "Hazardunit.v" +`include "Program_Counter.v" +`include "PC_Adder.v" +`include "mux2_1.v" +`include "mux3_1.v" +`include "Instruction_Memory.v" +`include "Control_Unit.v" +`include "Register_File.v" +`include "Sign_Extension.v" +`include "Alu.v" +`include "Data_Memory.v" +`include "Load_Extension.v" +`include "Store_Extension.v" +*/ + +module Pipeline(clk, rst,PC_D,Imm_Extension_E,RD1_E,RD2_E,Instruction_D,ReadData_W, Result_W); + + // Declaration of Inputs + input clk, rst; + input [31:0]PC_D,Imm_Extension_E;//Instruction_enable; + output [31:0] Instruction_D,ReadData_W,Result_W; + // input [31:0] instruction_fetch; +wire enable, clear, clear_d; +wire [31:0] PC_E; +wire [31:0]Instruction_E; +wire [4:0]RS1_E,RS2_E,RD_E,RD_M,RD_W; +input [31:0]RD1_E,RD2_E; +wire RegWrite_E,RegWrite_M,RegWrite_W; +wire MemWrite_E,MemWrite_M; +wire Result_Select_E,Result_Select_M,Result_Select_W; +wire Branch_E, Jump_E, Rs2_Select_E, PC_Select_E; +wire [31:0]PCTarget_E; +wire [31:0]Alu_Result_M,Alu_Result_W; +wire [31:0]WriteData_M; +wire [1:0] ForwardA_E, ForwardB_E; +wire [2:0] Operation_M; + // Module Initiation + // Fetch Stage + Fetch_cycle Fetch(.clk(clk), + .rst(rst), + .enable(enable), + .clear_d(clear_d), + .PC_Select_E(PC_Select_E), + .PCTarget_E(PCTarget_E), + .Instruction_D(Instruction_D), + .PC_D(PC_D) + // .instruction_fetch(instruction_fetch), + // .Instruction_enable(Instruction_enable) + ); + + // Decode Stage + Decode_cycle Decode(.clk(clk), + .rst(rst), + .clear(clear), + .RegWrite_W(RegWrite_W), + .RD_W(RD_W), + .Instruction_D(Instruction_D), + .PC_D(PC_D), + .Result_W(Result_W), + .RegWrite_E(RegWrite_E), + .MemWrite_E(MemWrite_E), + .Result_Select_E(Result_Select_E), + .Branch_E(Branch_E), + .Jump_E(Jump_E), + .Rs2_Select_E(Rs2_Select_E), + .RD1_E(RD1_E), + .RD2_E(RD2_E), + .Imm_Extension_E(Imm_Extension_E), + .RS1_E(RS1_E), + .RS2_E(RS2_E), + .RD_E(RD_E), + .PC_E(PC_E), + .Instruction_E(Instruction_E) + ); + + // Execute Stage + Execute_cycle Execute(.clk(clk), + .rst(rst), + .RegWrite_E(RegWrite_E), + .MemWrite_E(MemWrite_E), + .Result_Select_E(Result_Select_E), + .Branch_E(Branch_E), + .Jump_E(Jump_E), + .Rs2_Select_E(Rs2_Select_E), + .RD1_E(RD1_E), + .RD2_E(RD2_E), + .Imm_Extension_E(Imm_Extension_E), + .Instruction_E(Instruction_E), + .RD_E(RD_E), + .PC_E(PC_E), + .Result_W(Result_W), + .ForwardA_E(ForwardA_E), + .ForwardB_E(ForwardB_E), + .PC_Select_E(PC_Select_E), + .RegWrite_M(RegWrite_M), + .MemWrite_M(MemWrite_M), + .Result_Select_M(Result_Select_M), + .RD_M(RD_M), + .WriteData_M(WriteData_M), + .Alu_Result_M(Alu_Result_M), + .PCTarget_E(PCTarget_E), + .Operation_M(Operation_M) + ); + + // Memory Stage + Memory_cycle Memory(.clk(clk), + .rst(rst), + .RegWrite_M(RegWrite_M), + .MemWrite_M(MemWrite_M), + .Result_Select_M(Result_Select_M), + .RD_M(RD_M), + .WriteData_M(WriteData_M), + .Alu_Result_M(Alu_Result_M), + .RegWrite_W(RegWrite_W), + .Result_Select_W(Result_Select_W), + .RD_W(RD_W), + .Alu_Result_W(Alu_Result_W), + .ReadData_W(ReadData_W), + .Operation_M(Operation_M) + ); + + // Write Back Stage + Writeback_cycle WriteBack( + .Result_Select_W(Result_Select_W), + .Alu_Result_W(Alu_Result_W), + .ReadData_W(ReadData_W), + .Result_W(Result_W) + ); + + // Hazard Detection Unit + Hazardunit Hazard_Detection_Unit(.clear(clear), + .clear_d(clear_d), + .enable(enable), + .ForwardA_E(ForwardA_E), + .ForwardB_E(ForwardB_E), + .opcode_D(Instruction_D[6:0]), + .opcode_E(Instruction_E[6:0]), + .RS1_E(RS1_E), + .RS2_E(RS2_E), + .RD_E(RD_E), + .RD_M(RD_M), + .RD_W(RD_W), + .RS1_D(Instruction_D[19:15]), + .RS2_D(Instruction_D[24:20]), + .RegWrite_M(RegWrite_M), + .RegWrite_W(RegWrite_W), + .Result_Select_E(Result_Select_E), + .PC_Select_E(PC_Select_E) + ); + +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Pipeline_tb.v b/RISC_V/Pipeline/Pipeline_tb.v new file mode 100644 index 0000000..aa49574 --- /dev/null +++ b/RISC_V/Pipeline/Pipeline_tb.v @@ -0,0 +1,179 @@ +module Pipeline_tb(); +reg clk, rst; +integer k,l; + +Pipeline riscv(.clk(clk),.rst(rst)); + +initial + begin + rst= 1; + #2 rst = 0; + repeat (20) + begin + #5 clk=0;#5 clk=1; + end + end + +initial + begin + for (k=0; k<31; k=k+1) + begin + riscv.Decode.Registers.Register[k] = k; + end + for (l = 0; l <1024 ; l = l+1) + begin + riscv.Memory.Data_Memory.mem[l] = l; + end + end + + initial begin + /* +//Control and data +//riscv.PC_Reg = 10'b0; + riscv.Fetch.IMem.Mem[0] = 32'h00208AB3; // ADD X21 X1 X2 + riscv.Fetch.IMem.Mem[4] = 32'h00B08113; // ADDI X2 X1 11 + riscv.Fetch.IMem.Mem[8] = 32'h015A49B3; // XOR X19 X20 X21 + riscv.Fetch.IMem.Mem[12] = 32'hFE059AE3; // BNE X13 X0 -12 + riscv.Fetch.IMem.Mem[16] = 32'h41078733; // SUB X14, X15, X16 +*/ + +/* +//Signed and Unsigned + riscv.Fetch.IMem.Mem[0] = 32'hFFF4A513; // SLTI X10,X9,-1 + riscv.Fetch.IMem.Mem[4] = 32'hFFF4B513; // SLTUI X10,X9,-1 +*/ + +/* +riscv.Fetch.IMem.Mem[0] = 32'h00158693; // ADDI X13, X11,1 +riscv.Fetch.IMem.Mem[4] = 32'h41078733; // SUB X14, X15, X16 +riscv.Fetch.IMem.Mem[8] = 32'hC2211363; // BEQ X0, X0, 0 +riscv.Fetch.IMem.Mem[12] = 32'h0128F833; // AND X16, X17, X18 +riscv.Fetch.IMem.Mem[16] = 32'h015A49B3; // XOR X19, X20, X21 +*/ +/* +riscv.Fetch.IMem.Mem[0] = 32'h00108113; // ADDI X2,X1,1 +riscv.Fetch.IMem.Mem[4] = 32'h00508167; // JALR X2,X1,5 +*/ +/* +riscv.Fetch.IMem.Mem[0] = 32'h00108113; // ADDI X2,X1,1 +riscv.Fetch.IMem.Mem[4] = 32'h22200CEF; // JAL X25,0X00000111 +*/ +/* +riscv.Fetch.IMem.Mem[0] = 32'h00108113; // ADDI X2,X1,1 +riscv.Fetch.IMem.Mem[4] = 32'h12346B17; // AUIPC X22,12346 +*/ + +/* +riscv.Fetch.IMem.Mem[0] = 32'h00108113; // ADDI X2,X1,1 +riscv.Fetch.IMem.Mem[4] = 32'h12345B37; // LUI X22,12345 + +/* +//Store, R, Load + //riscv.PCF = 32'h00000000; + riscv.Fetch.IMem.Mem[0] = 32'h01508123; // SB X21,X1,2 + riscv.Fetch.IMem.Mem[4] = 32'h01619223; // SH X22,X3,4 + riscv.Fetch.IMem.Mem[8] = 32'h0172A323; // SW X23,X5,6 + riscv.Fetch.IMem.Mem[12] = 32'h0083AC33; // SLT X24,X7,8 + riscv.Fetch.IMem.Mem[16] = 32'h00A4BCB3; // SLTU X25,X9,10 + riscv.Fetch.IMem.Mem[20] = 32'h00C5CD33; // XOR X26,X11,12 + riscv.Fetch.IMem.Mem[24] = 32'h00E6DDB3; // SRL X27,X13,14 + riscv.Fetch.IMem.Mem[28] = 32'h4107DE33; // SRA X28,X15,16 + riscv.Fetch.IMem.Mem[32] = 32'h0128EEB3; // OR X29,X17,18 + riscv.Fetch.IMem.Mem[36] = 32'h0149FF33; // AND X30,X19,20 + riscv.Fetch.IMem.Mem[40] = 32'h00110083; // LB X1,X2,1 + riscv.Fetch.IMem.Mem[44] = 32'h00321183; // LH X3,X4,3 + riscv.Fetch.IMem.Mem[48] = 32'h00532283; // LW X5,X6,5 +*/ +/* +//LOAD TYPE + riscv.Fetch.IMem.Mem[0] = 32'h00110083; // LB X1,X2,1 + riscv.Fetch.IMem.Mem[4] = 32'h00121183; // LH X3,X4,1 + riscv.Fetch.IMem.Mem[8] = 32'h00132283; // LW X5,X6,1 + riscv.Fetch.IMem.Mem[12] = 32'h00144383; // LBU X7,X8,1 + riscv.Fetch.IMem.Mem[16] = 32'h00155483; // LHU X9,X10,1 +*/ +/* +//STORE TYPE + riscv.Fetch.IMem.Mem[0] = 32'h00110023; // SB X2,X1,0 + riscv.Fetch.IMem.Mem[4] = 32'h00321123; // SH X4,X3,2 + riscv.Fetch.IMem.Mem[8] = 32'h005321A3; // SW X6,X5,3 +*/ + +//REGISTER TYPE + riscv.Fetch.IMem.Mem[0] = 32'h00208AB3; // ADD X21,X1,2 + riscv.Fetch.IMem.Mem[4] = 32'h40418B33; // SUB X22,X3,4 + riscv.Fetch.IMem.Mem[8] = 32'h00629BB3; // SLL X23,X5,6 + riscv.Fetch.IMem.Mem[12] = 32'h0083AC33; // SLT X24,X7,8 + riscv.Fetch.IMem.Mem[16] = 32'h00A4BCB3; // SLTU X25,X9,10 + riscv.Fetch.IMem.Mem[20] = 32'h00C5CD33; // XOR X26,X11,12 + riscv.Fetch.IMem.Mem[24] = 32'h00E6DDB3; // SRL X27,X13,14 + riscv.Fetch.IMem.Mem[28] = 32'h4107DE33; // SRA X28,X15,16 + riscv.Fetch.IMem.Mem[32] = 32'h0128EEB3; // OR X29,X17,18 + riscv.Fetch.IMem.Mem[36] = 32'h0149FF33; // AND X30,X19,20 + + +/* +//IMMEDIATE INSTRUCTIONS + riscv.Fetch.IMem.Mem[0] = 32'h00108113; // ADDI X2,X1,1 + riscv.Fetch.IMem.Mem[4] = 32'h00219213; // SLLI X4,X3,2 + riscv.Fetch.IMem.Mem[8] = 32'h0032A313; // SLTI X6,X5,3 + riscv.Fetch.IMem.Mem[12] = 32'h8003B413; // SLTUI X8,X7,'h800 + riscv.Fetch.IMem.Mem[16] = 32'h0054C513; // XORI X10,X9,5 + riscv.Fetch.IMem.Mem[20] = 32'h0065D613; // SRLI X12,X11,6 + riscv.Fetch.IMem.Mem[24] = 32'h0076D713; // SRAI X14,X13,7 + riscv.Fetch.IMem.Mem[28] = 32'h0087E813; // ORI X16,X15,8 + riscv.Fetch.IMem.Mem[32] = 32'h0098F913; // ANDI X18,X17,9 +*/ + /* + riscv.Fetch.IMem.Mem[0] = 32'h00200193; // ADDI X3,X0,2 + riscv.Fetch.IMem.Mem[4] = 32'hFFE00193; // ADDI X3,X0,-2 +*/ + /* + //control hazard + riscv.PC_Reg = 10'b0; + riscv.Instructionmemory.IMem[0] = 32'h00158693; // ADDI X13, X11,1 + riscv.Instructionmemory.IMem[4] = 32'h41078733; // SUB X14, X15, X16 + riscv.Instructionmemory.IMem[8] = 32'hFE0698E3; // BNE X13, X0, -8 + // riscv.Instructionmemory.IMem[8] = 32'h00069063; // BNE X13, X0, 0 + riscv.Instructionmemory.IMem[12] = 32'h0128F833; // AND X16, X17, X18 + riscv.Instructionmemory.IMem[16] = 32'h015A49B3; // XOR X19, X20, X21 + */ + /* + riscv.PC_Reg = 10'b0; + riscv.Instructionmemory.IMem[0] = 32'h00A08113; // ADDI X2, X1,10 + riscv.Instructionmemory.IMem[4] = 32'h00B18233; // ADD X4, X3,X11 + riscv.Instructionmemory.IMem[8] = 32'h00C2E333; // OR X6, X5,X12 + riscv.Instructionmemory.IMem[12] = 32'h015822A3; // STORE OPERATION SW X8, X21, 5 + riscv.Instructionmemory.IMem[16] = 32'h00A3A403; // LOAD OPERATION LW X8, X7, 10 + riscv.Instructionmemory.IMem[20] = 32'h00D49533; // SLL X10, X9, X13 + riscv.Instructionmemory.IMem[24] = 32'hFEF718E3; // BNE X14, X15,8 + riscv.Instructionmemory.IMem[28] = 32'h00000013; // ADD1 X0, X0 0 + */ + /*riscv.Instructionmemory.IMem[4] = 32'h00A18213; + riscv.Instructionmemory.IMem[8] = 32'h00A28313; + riscv.Instructionmemory.IMem[12] = 32'h00A38413; + riscv.Instructionmemory.IMem[16] = 32'h00A48513; + riscv.Instructionmemory.IMem[20] = 32'h00A58613; + riscv.Instructionmemory.IMem[24] = 32'h00000013; + riscv.Instructionmemory.IMem[28] = 32'h00A18113; + riscv.Instructionmemory.IMem[32] = 32'h00A10213; + riscv.Instructionmemory.IMem[36] = 32'h00000013; + riscv.Instructionmemory.IMem[40] = 32'h00A08113; + riscv.Instructionmemory.IMem[32] = 32'h00000013; + riscv.Instructionmemory.IMem[36] = 32'h00000013; + riscv.Instructionmemory.IMem[40] = 32'h00000013; + riscv.Instructionmemory.IMem[44] = 32'h00000013; + riscv.Instructionmemory.IMem[48] = 32'h00000013; + + + riscv.Instructionmemory.IMem[0] = 32'h00A08113; + riscv.Instructionmemory.IMem[4] = 32'h00F18213; + riscv.Instructionmemory.IMem[8] = 32'h00B28333; + riscv.Instructionmemory.IMem[12] = 32'h40C38433; + riscv.Instructionmemory.IMem[16] = 32'h00D4F533; + */ + end + initial begin + #200 $finish; + end +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Program_Counter.v b/RISC_V/Pipeline/Program_Counter.v new file mode 100644 index 0000000..ab28607 --- /dev/null +++ b/RISC_V/Pipeline/Program_Counter.v @@ -0,0 +1,19 @@ +module Program_Counter(clk,rst,enable,PC,PC_Next); +input clk, rst, enable; +input [31:0]PC_Next; +output reg [31:0]PC; + +wire [31:0]PC_temp; + +assign PC_temp = PC; + +always@(posedge clk or posedge enable or posedge rst) + begin + if(rst==1) + PC <= 32'h00000000; + else if(enable == 1) // for Data Hazard + PC <= PC_temp; + else + PC <= PC_Next; + end +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Register_File.v b/RISC_V/Pipeline/Register_File.v new file mode 100644 index 0000000..7965751 --- /dev/null +++ b/RISC_V/Pipeline/Register_File.v @@ -0,0 +1,21 @@ +module Register_File(clk,rst,WE3,WD3,A1,A2,A3,RD1,RD2); + + input clk,rst,WE3; + input [4:0]A1,A2,A3; + input [31:0]WD3; + output [31:0]RD1,RD2; + + reg [31:0] Register [31:0]; + + always @ (posedge clk) + begin + if(WE3 & (A3 != 5'b00000)) + Register[A3] <= WD3; + end + + assign RD1 = (rst==1'b1) ? 32'h00000000 : Register[A1]; + assign RD2 = (rst==1'b1) ? 32'h00000000 : Register[A2]; + initial begin + Register[0] = 32'h00000000; + end +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Sign_Extension.v b/RISC_V/Pipeline/Sign_Extension.v new file mode 100644 index 0000000..186e766 --- /dev/null +++ b/RISC_V/Pipeline/Sign_Extension.v @@ -0,0 +1,22 @@ +module Sign_Extension(Instruction, Imm); +input [31:0] Instruction; +output [31:0]Imm; + +parameter [6:0]r_to_imm = 7'b0010011, + ld = 7'b0000011, + store = 7'b0100011, + // upperimm = 7'b0110111, + // upperjump = 7'b1101111, + branch = 7'b1100011, + lui = 7'b0110111, + Auipc = 7'b0010111, + jal = 7'b1101111, + jalr = 7'b1100111; + + +assign Imm = (Instruction[6:0] == r_to_imm || Instruction[6:0] == ld || Instruction[6:0] == jalr) ? {{20{Instruction [31]}}, Instruction[31:20]} : + (Instruction[6:0] == store) ? {{20{Instruction [31]}}, Instruction[31:25], Instruction [11:7]}: + (Instruction[6:0] == branch) ? {{19{Instruction [31]}}, Instruction[31], Instruction [7], Instruction[30:25], Instruction [11:8],1'b0} : + (Instruction[6:0] == lui || Instruction[6:0] == Auipc) ? {Instruction[31:12], {12'b0}} : + (Instruction[6:0] == jal) ? {{12{Instruction[31]}}, Instruction[19:12], Instruction[20], Instruction[30:21],1'b0}: 32'b0; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Store_Extension.v b/RISC_V/Pipeline/Store_Extension.v new file mode 100644 index 0000000..cd2bb8c --- /dev/null +++ b/RISC_V/Pipeline/Store_Extension.v @@ -0,0 +1,9 @@ +module Store_Extension(WriteData_E_temp,Operation,WriteData_E); +input [31:0] WriteData_E_temp; +input [2:0]Operation; +output [31:0] WriteData_E; + +assign WriteData_E = (Operation == 3'b000)? WriteData_E_temp[7:0] : + (Operation == 3'b001)? WriteData_E_temp[15:0]: + (Operation == 3'b010)? WriteData_E_temp : 32'hxxxxxxxx; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/Writeback_cycle.v b/RISC_V/Pipeline/Writeback_cycle.v new file mode 100644 index 0000000..3a85e7d --- /dev/null +++ b/RISC_V/Pipeline/Writeback_cycle.v @@ -0,0 +1,15 @@ +module Writeback_cycle(Result_Select_W, Alu_Result_W, ReadData_W, Result_W); + +// Declaration of Inputs and Outputs +input Result_Select_W; +input [31:0] Alu_Result_W, ReadData_W; + +output [31:0] Result_W; + +// Declaration of Module +mux2_1 result_mux(.a(Alu_Result_W), + .b(ReadData_W), + .s(Result_Select_W), + .y(Result_W) + ); +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/mux2_1.v b/RISC_V/Pipeline/mux2_1.v new file mode 100644 index 0000000..a0cf5e6 --- /dev/null +++ b/RISC_V/Pipeline/mux2_1.v @@ -0,0 +1,6 @@ +module mux2_1(y,s,a,b); +input [31:0]a,b; +input s; +output [31:0]y; +assign y = (s==0)?a:b; +endmodule \ No newline at end of file diff --git a/RISC_V/Pipeline/mux3_1.v b/RISC_V/Pipeline/mux3_1.v new file mode 100644 index 0000000..04e7f84 --- /dev/null +++ b/RISC_V/Pipeline/mux3_1.v @@ -0,0 +1,8 @@ +module mux3_1(a,b,c,s,y); +input [31:0] a,b,c; +input [1:0] s; +output [31:0] y; +assign y = (s == 2'b00) ? a: + (s == 2'b01) ? b: + (s == 2'b10) ? c: 32'hxxxxxxxx; +endmodule \ No newline at end of file