RISC_V/RISC_V/Pipeline/Writeback_cycle.v

module Writeback_cycle(Result_Select_W, Alu_Result_W, ReadData_W, Result_W);

// Declaration of Inputs and Outputs
input Result_Select_W;
input [31:0] Alu_Result_W, ReadData_W;

output [31:0] Result_W;

// Declaration of Module
mux2_1 result_mux(.a(Alu_Result_W),
                  .b(ReadData_W),
                  .s(Result_Select_W),
                  .y(Result_W)
                 );
endmodule