AXI-Verification architecture, functional coverage and assertions based coverage code
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  1. //driver
  2. class driver extends uvm_driver #(packet);
  3. `uvm_component_utils(driver)
  4. virtual axi_if vif;
  5. packet pkt;
  6. function new(string name="driver", uvm_component parent=null);
  7. super.new(name, parent);
  8. endfunction
  9. virtual function void build_phase(uvm_phase phase);
  10. super.build_phase(phase);
  11. pkt=packet::type_id::create("pkt");
  12. if(!uvm_config_db#(virtual axi_if)::get(this,"","vif",vif))
  13. `uvm_error("drv","Unable to access Interface");
  14. endfunction
  15. task reset_dut();
  16. repeat (2) begin
  17. //write address channel
  18. vif.awvalid <= 0;
  19. vif.awready <= 0;
  20. vif.awid <= 0;
  21. vif.awlen <= 0;
  22. vif.awsize <= 0;
  23. vif.awaddr <= 0;
  24. vif.awburst <= 0;
  25. //write data channel (w)
  26. vif.wvalid <= 0;
  27. vif.wready <= 0;
  28. vif.wid <= 0;
  29. vif.wdata <= 0;
  30. vif.wstrb <= 0;
  31. vif.wlast <= 0;
  32. //write response channel (b)
  33. vif.bready <= 0;
  34. vif.bvalid <= 0;
  35. vif.bid <= 0;
  36. vif.bresp <= 0;
  37. ///////////////read address channel (ar)
  38. vif.arvalid <= 0;
  39. vif.arready <= 0;
  40. vif.arid <= 0;
  41. vif.arlen <= 0;
  42. vif.arsize <= 0;
  43. vif.araddr <= 0;
  44. vif.arburst <= 0;
  45. /////////// read data channel (r)
  46. vif.rvalid <= 0;
  47. vif.rready <= 0;
  48. vif.rid <= 0;
  49. vif.rdata <= 0;
  50. vif.rstrb <= 0;
  51. vif.rlast <= 0;
  52. vif.rresp <= 0;
  53. //1 clk delay
  54. @(posedge vif.clk);
  55. `uvm_info(get_type_name(),"*** Reset Applied by driver ***",UVM_MEDIUM)
  56. end
  57. endtask
  58. task write();
  59. if(pkt.op==WRITE)
  60. begin
  61. //write address channel
  62. vif.awvalid <= pkt.awvalid ;
  63. vif.awready <= pkt.awready ;
  64. vif.awid <= pkt.awid ;
  65. vif.awlen <= pkt.awlen ;
  66. vif.awsize <= pkt.awsize ;
  67. vif.awaddr <= pkt.awaddr ;
  68. vif.awburst <= pkt.awburst ;
  69. //write data channel (w)
  70. vif.wvalid <= pkt.wvalid ;
  71. vif.wready <= pkt.wready ;
  72. vif.wid <= pkt.wid ;
  73. vif.wdata <= pkt.wdata ;
  74. vif.wstrb <= pkt.wstrb ;
  75. vif.wlast <= pkt.wlast ;
  76. //write response channel (b)
  77. vif.bready <= pkt.bready ;
  78. vif.bvalid <= pkt.bvalid ;
  79. vif.bid <= pkt.bid ;
  80. //1 clk delay
  81. @(posedge vif.clk);
  82. `uvm_info(get_type_name(),"*** write signals are drived to DUT ***",UVM_MEDIUM)
  83. vif.bresp <= pkt.bresp ; end
  84. endtask
  85. task read();
  86. if(pkt.op == READ)begin
  87. ///////////////read address channar)
  88. vif.arvalid <= pkt.arvalid ;
  89. vif.arready <= pkt.arready ;
  90. vif.arid <= pkt.arid ;
  91. vif.arlen <= pkt.arlen ;
  92. vif.arsize <= pkt.arsize ;
  93. vif.araddr <= pkt.araddr ;
  94. vif.arburst <= pkt.arburst ;
  95. /////////// read data channel (r)
  96. vif.rvalid <= pkt.rvalid ;
  97. vif.rready <= pkt.rready ;
  98. vif.rid <= pkt.rid ;
  99. vif.rdata <= pkt.rdata ;
  100. vif.rstrb <= pkt.rstrb ;
  101. vif.rlast <= pkt.rlast ;
  102. vif.rresp <= pkt.rresp ;
  103. //1 clk delay
  104. @(posedge vif.clk);
  105. `uvm_info(get_type_name(),"*** read signals are drived to DUT ***",UVM_MEDIUM)
  106. end
  107. endtask
  108. virtual task run_phase(uvm_phase phase);
  109. reset_dut();
  110. forever begin
  111. seq_item_port.get_next_item(pkt);
  112. `uvm_info(get_type_name(),"*** Driver Received the transaction by sequencer ***",UVM_MEDIUM)
  113. if(pkt.op==RESET) begin
  114. reset_dut();
  115. end
  116. //Write operation support
  117. else if(pkt.op == WRITE) begin
  118. write();
  119. `uvm_info(get_type_name(),"*** WRITE packet is received in driver ***",UVM_MEDIUM)
  120. end
  121. else if(pkt.op == READ) begin
  122. read();
  123. `uvm_info(get_type_name(),"*** READ packet is received in driver ***",UVM_MEDIUM)
  124. end
  125. //put read drive logic here
  126. seq_item_port.item_done();
  127. end
  128. endtask
  129. endclass