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AXI-Verification
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AXI-Verification architecture, functional coverage and assertions based coverage code
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AXI-Verification/axi_driver.sv

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  1. //driver

  2. class driver extends uvm_driver #(packet);

  3.  `uvm_component_utils(driver)

  4. 

  5. virtual axi_if vif;

  6. packet pkt;

  7.   

  8.   function new(string name="driver", uvm_component parent=null);

  9.  super.new(name, parent);

  10.  endfunction

  11. 

  12.   virtual function void build_phase(uvm_phase phase);

  13.     super.build_phase(phase);

  14.     pkt=packet::type_id::create("pkt");

  15.     if(!uvm_config_db#(virtual axi_if)::get(this,"","vif",vif))

  16.       `uvm_error("drv","Unable to access Interface");

  17.   endfunction

  18.  

  19.   task reset_dut();

  20.     repeat (3) begin

  21.       //write address channel

  22.   		vif.awvalid 	<= 0;

  23.   		vif.awready		<= 0;

  24.   		vif.awid 		<= 0;

  25.   		vif.awlen 		<= 0;

  26.  		vif.awsize 		<= 0;

  27.  		vif.awaddr 		<= 0;   

  28.         vif.awburst		<= 0;

  29.       //write data channel (w)

  30.   		vif.wvalid 		<= 0;

  31.   		vif.wready		<= 0;

  32.   		vif.wid 		<= 0;

  33.   		vif.wdata 		<= 0;

  34.  		vif.wstrb 		<= 0;

  35.  		vif.wlast 		<= 0; 

  36.       //write response channel (b)

  37.    		vif.bready 		<= 0;

  38.   		vif.bvalid 		<= 0;

  39.  		vif.bid 		<= 0;

  40.  		vif.bresp 		<= 0;      

  41.   	  ///////////////read address channel (ar)      

  42.   		vif.arvalid 	<= 0;

  43.   		vif.arready		<= 0;

  44.   		vif.arid 		<= 0;

  45.   		vif.arlen 		<= 0;

  46.  		vif.arsize 		<= 0;

  47.  		vif.araddr 		<= 0;   

  48.         vif.arburst		<= 0;      

  49. 	 /////////// read data channel (r)      

  50.    		vif.rvalid 	<= 0;

  51.   		vif.rready		<= 0;

  52.   		vif.rid 		<= 0;

  53.   		vif.rdata 		<= 0;

  54.  		vif.rstrb 		<= 0;

  55.  		vif.rlast 		<= 0;   

  56.         vif.rresp		<= 0;         

  57.         

  58.       //1 clk delay

  59.       @(posedge vif.clk);

  60.       `uvm_info(get_type_name(),"*** Reset Applied by driver  ***",UVM_MEDIUM)      

  61.   end

  62.  endtask

  63.       

  64.  virtual task run_phase(uvm_phase phase);

  65.     reset_dut();    

  66.     forever begin

  67.       seq_item_port.get_next_item(pkt);

  68.       `uvm_info(get_type_name(),"*** Driver Received the transaction by sequencer  ***",UVM_MEDIUM)     

  69.       

  70. //---------------------------------------------------------

  71. //----------------------------------------------------------

  72. ////////////////////////////////////////      WRITE ADDRESS CHANNEL

  73. 

  74. task write_address_pkt_channel();

  75. 

  76. 	`uvm_info("MASTER_DRIVER",$sformatf("PRINTING FROM DRIVER \n %s",pkt.sprint()),UVM_HIGH)

  77. 	

  78. 	case (pkt.awburst)

  79. 

  80. 		2'b00 : write_address_fixed_burst;

  81. 		2'b01 : write_address_incr_burst;

  82. 		2'b10 : write_address_wrap_burst;

  83. 

  84. 	endcase

  85. 		

  86. 

  87. endtask

  88. ////////////////////////////////////////  WRAP address BURST

  89. task write_address_wrap_burst();

  90. begin

  91.       int start_addr=(`INT pkt.awaddr/((pkt.awlen+1)*(2**pkt.awsize)))*((pkt.awlen+1)*(2**pkt.awsize));

  92. int end_addr=(start_addr + ((pkt.awlen+1)*(2**pkt.awsize)));

  93. 

  94. for (int i=0; i< (pkt.awlen+1);i++)

  95. begin

  96. vif.awaddr <= pkt.awaddr;

  97. 

  98. if(vif.awaddr == end_addr)

  99. 	vif.awaddr <= start_addr;

  100. else

  101. vif.awaddr <= vif.awaddr+ (2**vif.awsize);

  102. 		vif.awid   <= pkt.awid;

  103. 		vif.awvalid<= 1;

  104. 		wait(vif.awready);

  105. 		vif.awvalid<=0;

  106. end

  107. write_data_wrap_burst();

  108. endtask

  109. ///////////////////////////////////////        wrapBURST

  110. 

  111. task write_data_wrap_burst();

  112. 

  113. if (vif.awvalid || vif.wvalid ||( vif.awvalid &&vif.wvalid))

  114. 	foreach(pkt.wdata[i])

  115. 	begin

  116. 	

  117. 		case (pkt.wstrobe[i])

  118. 				

  119. 			4'b0001 : vif.wdata [7:0]   <= pkt.wdata[i];

  120. 			4'b0010 : vif.wdata [15:8]  <= pkt.wdata[i];

  121. 			4'b0100 : vif.wdata [23:16] <= pkt.wdata[i];

  122. 			4'b1000 : vif.wdata [31:24] <= pkt.wdata[i];

  123. 			4'b0011 : vif.wdata [15:0]  <= pkt.wdata[i];

  124. 			4'b1100 : vif.wdata [31:16] <= pkt.wdata[i];

  125. 			4'b1110 : vif.wdata [31:8]  <= pkt.wdata[i];

  126. 			4'b1111 : vif.wdata [31:0]  <= pkt.wdata[i];

  127. 	

  128. 		endcase

  129. 

  130. 		vif.wstrobe <= pkt.wstrobe[i];

  131. 		vif.wid <= pkt.wid;

  132. 		

  133. 		if (i == pkt.awlen )

  134. 			vif.wlast <= 1;

  135. 		else 

  136. 			vif.wlast <= 0;

  137. 		

  138. 		vif.wvalid <= 1;

  139. 

  140. 

  141. 		wait (vif.wready);

  142. 

  143. 		vif.wlast <= 0;

  144. 		vif.wvalid <= 0;

  145. 		

  146. 

  147. 	end

  148.        	write_response_channel ();

  149. endtask

  150. 

  151. 

  152. 

  153. 

  154. ////////////////////////////////////////  INCR address    INCREMENT BURST

  155. 

  156. task write_address_incr_burst();

  157. 	vif.awlen <=pkt.awlen;

  158. 	for(int i=0; i<(awlen +1);i++)

  159. 	begin

  160. 		vif.awaddr<=pkt.awaddr;

  161.         	vif.awid   <= pkt.awid;

  162. 		vif.awvalid<= 1;

  163. 		pkt.awaddr<= pkt.awaddr +(2**vif.awsize);

  164. 		wait(vif.awready);

  165. 		vif.awvalid<=0;

  166. 

  167. 	end

  168. write_data_incr_burst();

  169. endtask

  170. ///////////////////////////////////////        write data INCREMENT BURST

  171. 

  172. task write_data_incr_burst();

  173. 

  174. if (vif.awvalid || vif.wvalid ||( vif.awvalid &&vif.wvalid))

  175. 	foreach(pkt.wdata[i])

  176. 	begin

  177. 	

  178. 		case (pkt.wstrobe[i])

  179. 				

  180. 			4'b0001 : vif.wdata [7:0]   <= pkt.wdata[i];

  181. 			4'b0010 : vif.wdata [15:8]  <= pkt.wdata[i];

  182. 			4'b0100 : vif.wdata [23:16] <= pkt.wdata[i];

  183. 			4'b1000 : vif.wdata [31:24] <= pkt.wdata[i];

  184. 			4'b0011 : vif.wdata [15:0]  <= pkt.wdata[i];

  185. 			4'b1100 : vif.wdata [31:16] <= pkt.wdata[i];

  186. 			4'b1110 : vif.wdata [31:8]  <= pkt.wdata[i];

  187. 			4'b1111 : vif.wdata [31:0]  <= pkt.wdata[i];

  188. 	

  189. 		endcase

  190. 

  191. 		vif.wstrobe <= pkt.wstrobe[i];

  192. 		vif.wid <= pkt.wid;

  193. 		

  194. 		if (i == pkt.awlen )

  195. 			vif.wlast <= 1;

  196. 		else 

  197. 			vif.wlast <= 0;

  198. 		

  199. 		vif.wvalid <= 1;

  200. 

  201. 

  202. 		wait (vif.wready);

  203. 

  204. 		vif.wlast <= 0;

  205. 		vif.wvalid <= 0;

  206. 		

  207. 

  208. 	end

  209.        	write_response_channel ();

  210. endtask

  211. ///////////////write address fixed burst

  212. task write_address_fixed_burst ();

  213. 	vif.awlen  <= 4'b0000;

  214.         vif.awid   <= pkt.awid;

  215. 	vif.awaddr <= pkt.awaddr;

  216. 	vif.awvalid<= 1;

  217. wait(vif.awready);

  218. 	vif.awvalid<=0;

  219. 	write_data_fixed_burst();

  220. 

  221. endtask

  222. 

  223. 

  224. //////////////////////////////////////        write data first burst

  225. 

  226. task write_data_fixed_burst ();

  227. if (vif.awvalid || vif.wvalid ||( vif.awvalid &&vif.wvalid))

  228. 	foreach(pkt.wdata[i])

  229. 	begin

  230. 		

  231. 		case (pkt.awsize)

  232. 	

  233. 			3'b000 : vif.wdata[7:0] <= pkt.wdata[i];

  234. 			3'b001 : vif.wdata[15:0] <= pkt.wdata[i];

  235. 			3'b010 : vif.wdata[31:0] <= pkt.wdata[i];

  236. 			3'b011 : vif.wdata[63:0] <= pkt.wdata[i];

  237. 			3'b100 : vif.wdata[127:0] <= pkt.wdata[i];

  238. 			3'b101 : vif.wdata[255:0] <= pkt.wdata[i];

  239. 			3'b110 : vif.wdata[511:0] <= pkt.wdata[i];

  240. 			3'b110 : vif.wdata[1023:0] <= pkt.wdata[i];

  241. 

  242. 		

  243. 		endcase

  244. 		

  245. 		vif.wid <= pkt.wid;

  246. 		

  247. 		if (i == pkt.awlen)

  248. 			vif.wlast <= 1;

  249. 		else 

  250. 			vif.wlast <= 0;

  251. 			vif.wvalid <= 1;

  252. 		wait (vif.wready);

  253. 			vif.wlast <= 0;

  254. 			vif.wvalid <= 0;

  255. 		

  256. 

  257. 		end

  258. 	       	write_response_channel ();

  259. 

  260. endtask

  261. 

  262. 

  263. ///////////////////////////////////////     WRITE RESPONSE CHANNEL

  264. 

  265. task write_response_channel ();

  266. if (vif.awvalid && vif.awready && vif.awlast)

  267. 		

  268. 	wait(vif.bvalid)

  269. begin

  270. 		

  271. 	vif.bid = pkt.bid;

  272. 	vif.bresp = pkt.bresp;

  273. end	

  274. 	vif.bready <= 1;

  275. 	

  276. 	foreach (vif.wdata[i])

  277. 	begin	

  278. 		if (vif.awid == vif.bid)

  279. 		begin

  280. 			case (vif.bresp)

  281. 

  282. 				2'b00 : s = "Transaction OKAY";

  283. 				2'b01 : s = "Transaction FAILED";

  284. 				2'b10 : s = "SLAVE ERROR";

  285. 				2'b11 : s = "DEEOCDE ERROR";

  286. 			

  287. 			endcase

  288. 				

  289. 			`uvm_info("MASTER_DRIVER",$sformatf("\n\n \t\t\t\t\t\t %s RESPONSE FOR THE DATA \n",s),UVM_MEDIUM)

  290. 	

  291. 		end

  292. 	end

  293. 	

  294. 	vif.bready <= 0;

  295. 

  296. 

  297. endtask

  298. 

  299. ///////////////////////////////////////    READ ADDRESS CHANNEL

  300. 

  301. task read_address_pkt_channel();

  302. 

  303. 	`uvm_info("MASTER_DRIVER",$sformatf("PRINTING FROM DRIVER \n %s",pkt.sprint()),UVM_HIGH)

  304. 

  305. 	vif.arid <= pkt.arid;

  306. 	vif.araddr <= pkt.araddr;

  307. 	vif.arlen <= pkt.arlen;

  308. 	vif.arsize <= pkt.arsize;

  309. 	vif.arburst <= pkt.arburst;

  310. 	vif.arvalid <= 1;

  311. 

  312. 	@(vif);

  313. 		

  314. 	wait (vif.arready);

  315. 

  316. 	vif.arvalid <= 0;

  317. 	

  318. 	read_data_response_sema.put(1);

  319. 	pkt_sema.put(1);

  320. 

  321. 	repeat(2)

  322. 		@(vif);

  323. endtask

  324. ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

  325. ////////////////////////////////////////      WRITE ADDRESS CHANNEL

  326. 

  327. task read_address_pkt_channel();

  328. 

  329. 	`uvm_info("MASTER_DRIVER",$sformatf("PRINTING FROM DRIVER \n %s",pkt.sprint()),UVM_HIGH)

  330. 	

  331. 	case (pkt.awburst)

  332. 

  333. 		2'b00 : read_address_fixed_burst;

  334. 		2'b01 : read_address_incr_burst;

  335. 		2'b10 : read_address_wrap_burst;

  336. 

  337. 	endcase

  338. 		

  339. 

  340. endtask

  341. ////////////////////////////////////////  WRAP address BURST

  342. task read_address_wrap_burst();

  343. begin

  344.       int start_read_addr=(`INT pkt.araddr/((pkt.arlen+1)*(2**pkt.arsize)))*((pkt.arlen+1)*(2**pkt.arsize));

  345. int end_read_addr=(start_read_addr + ((pkt.arlen+1)*(2**pkt.arsize)));

  346. 

  347. for (int i=0; i< (pkt.arlen+1);i++)

  348. begin

  349. vif.araddr <= pkt.araddr;

  350. 

  351. if(vif.araddr == end_read_addr)

  352. 	vif.araddr <= start_read_addr;

  353. else

  354. vif.araddr <= vif.araddr+ (2**vif.arsize);

  355. 		vif.arid   <= pkt.arid;

  356. 		vif.arvalid<= 1;

  357. 		wait(vif.arready);

  358. 		vif.arvalid<=0;

  359. end

  360. read_data_wrap_burst();

  361. endtask

  362. ///////////////////////////////////////        wrapBURST

  363. 

  364. task read_data_wrap_burst();

  365. 

  366. if (vif.arvalid || vif.rvalid ||( vif.arvalid &&vif.rvalid))

  367. 		

  368. 	vif.arid <= pkt.rid;

  369. 		

  370. 		if (i == pkt.arlen )

  371. 			vif.rlast <= 1;

  372. 		else 

  373. 			vif.rlast <= 0;

  374. 		

  375. 		vif.rvalid <= 1;

  376. 

  377. 

  378. 		wait (vif.rready);

  379. 

  380. 		vif.rlast <= 0;

  381. 		vif.rvalid <= 0;

  382. 		

  383. 

  384. 	end

  385.        	if (vif.arvalid && vif.arready && vif.arlast)

  386. 		

  387. 	wait(vif.rvalid)

  388. begin

  389. 		

  390. 	vif.rid = pkt.rid;

  391. 	vif.rresp = pkt.rresp;

  392. end	

  393. 	vif.rready <= 1;

  394. 	

  395. 	foreach (vif.rdata[i])

  396. 	begin	

  397. 		if (vif.arid == vif.rid)

  398. 		begin

  399. 			case (vif.rresp)

  400. 

  401. 				2'b00 : s = "Transaction OKAY";

  402. 				2'b01 : s = "Transaction FAILED";

  403. 				2'b10 : s = "SLAVE ERROR";

  404. 				2'b11 : s = "DEEOCDE ERROR";

  405. 			

  406. 			endcase

  407. 				

  408. 		`uvm_info("MASTER_DRIVER",$sformatf("\n\n \t\t\t\t\t\t %s RESPONSE FOR THE DATA \n",s),UVM_MEDIUM)

  409. 	

  410. 		end

  411. 	end

  412. 	

  413. 	vif.rready <= 0;

  414. 

  415. endtask

  416. 

  417. 

  418. 

  419. 

  420. ////////////////////////////////////////  INCR address    INCREMENT BURST

  421. 

  422. task read_address_incr_burst();

  423. 	vif.arlen <=pkt.arlen;

  424. 	for(int i=0; i<(arlen +1);i++)

  425. 	begin

  426. 		vif.araddr<=pkt.araddr;

  427.         	vif.arid   <= pkt.arid;

  428. 		vif.arvalid<= 1;

  429. 		pkt.araddr<= pkt.araddr +(2**vif.arsize);

  430. 		wait(vif.arready);

  431. 		vif.arvalid<=0;

  432. 

  433. 	end

  434. read_data_incr_burst();

  435. endtask

  436. ///////////////////////////////////////        read data INCREMENT BURST

  437. 

  438. task read_data_incr_burst();

  439. 

  440. if (vif.arvalid || vif.rvalid ||( vif.arvalid &&vif.rvalid))

  441. 	vif.rid <= pkt.rid;

  442. 		

  443. 	for(int i=0; i<(arlen +1);i++)

  444. 	begin

  445. 		vif.rdata <= pkt.rdata;

  446. 		if (i == pkt.arlen )

  447. 			vif.rlast <= 1;

  448. 		else 

  449. 			vif.rlast <= 0;

  450. 		

  451. 		vif.rvalid <= 1;

  452. 

  453. 

  454. 		wait (vif.rready);

  455. 

  456. 		vif.rlast <= 0;

  457. 		vif.rvalid <= 0;

  458. 		

  459. 

  460. 	end

  461.        		if (vif.arvalid && vif.arready && vif.arlast)

  462. 		

  463. 	wait(vif.rvalid)

  464. begin

  465. 		

  466. 	vif.rid = pkt.rid;

  467. 	vif.rresp = pkt.rresp;

  468. end	

  469. 	vif.rready <= 1;

  470. 	

  471. 	foreach (vif.rdata[i])

  472. 	begin	

  473. 		if (vif.arid == vif.rid)

  474. 		begin

  475. 			case (vif.rresp)

  476. 

  477. 				2'b00 : s = "Transaction OKAY";

  478. 				2'b01 : s = "Transaction FAILED";

  479. 				2'b10 : s = "SLAVE ERROR";

  480. 				2'b11 : s = "DEEOCDE ERROR";

  481. 			

  482. 			endcase

  483. 				

  484. 		`uvm_info("MASTER_DRIVER",$sformatf("\n\n \t\t\t\t\t\t %s RESPONSE FOR THE DATA \n",s),UVM_MEDIUM)

  485. 	

  486. 		end

  487. 	end

  488. 	

  489. 	vif.rready <= 0;

  490. 	

  491. 

  492. endtask

  493. ///////////////read address fixed burst

  494. task read_address_fixed_burst ();

  495. begin

  496. 	vif.arlen  <= 4'b0000;

  497.         vif.arid   <= pkt.arid;

  498. 	vif.araddr <= pkt.araddr;

  499. 	vif.arvalid<= 1;

  500. wait(vif.arready);

  501. 	vif.arvalid<=0;

  502. 	end 

  503. 	read_data_fixed_burst();

  504. 

  505. endtask

  506. 

  507. 

  508. //////////////////////////////////////        read data first burst

  509. 

  510. task read_data_fixed_burst ();

  511. if (vif.arvalid || vif.rvalid ||( vif.arvalid &&vif.rvalid))

  512. 	foreach(pkt.rdata[i])

  513. 	begin

  514. 		

  515. 		case (pkt.arsize)

  516. 	

  517. 			3'b000 : vif.rdata[7:0] <= pkt.rdata[i];

  518. 			3'b001 : vif.rdata[15:0] <= pkt.rdata[i];

  519. 			3'b010 : vif.rdata[31:0] <= pkt.rdata[i];

  520. 			3'b011 : vif.rdata[63:0] <= pkt.rdata[i];

  521. 			3'b100 : vif.rdata[127:0] <= pkt.rdata[i];

  522. 			3'b101 : vif.rdata[255:0] <= pkt.rdata[i];

  523. 			3'b110 : vif.rdata[511:0] <= pkt.rdata[i];

  524. 			3'b110 : vif.rdata[1023:0] <= pkt.rdata[i];

  525. 

  526. 		

  527. 		endcase

  528. 		

  529. 		vif.rid <= pkt.rid;

  530. 		

  531. 		if (i == pkt.arlen)

  532. 			vif.rlast <= 1;

  533. 		else 

  534. 			vif.rlast <= 0;

  535. 			vif.rvalid <= 1;

  536. 		wait (vif.rready);

  537. 			vif.rlast <= 0;

  538. 			vif.rvalid <= 0;

  539. 		

  540. 

  541. 		end

  542. 	if (vif.arvalid && vif.arready && vif.arlast)

  543. 		

  544. 	wait(vif.rvalid)

  545. begin

  546. 		

  547. 	vif.rid = pkt.rid;

  548. 	vif.rresp = pkt.rresp;

  549. end	

  550. 	vif.rready <= 1;

  551. 	

  552. 	foreach (vif.rdata[i])

  553. 	begin	

  554. 		if (vif.arid == vif.rid)

  555. 		begin

  556. 			case (vif.rresp)

  557. 

  558. 				2'b00 : s = "Transaction OKAY";

  559. 				2'b01 : s = "Transaction FAILED";

  560. 				2'b10 : s = "SLAVE ERROR";

  561. 				2'b11 : s = "DEEOCDE ERROR";

  562. 			

  563. 			endcase

  564. 				

  565. 		`uvm_info("MASTER_DRIVER",$sformatf("\n\n \t\t\t\t\t\t %s RESPONSE FOR THE DATA \n",s),UVM_MEDIUM)

  566. 	

  567. 		end

  568. 	end

  569. 	

  570. 	vif.rready <= 0;

  571. 

  572. endtask

  573. //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------      

  574.       

  575.       if(pkt.op==RESET) begin

  576.        reset_dut();

  577.      end     

  578.       //Write operation support

  579.       else if(pkt.op == WRITE) begin  

  580.         `uvm_info(get_type_name(),"*** WRITE packet is received in driver  ***",UVM_MEDIUM) 

  581. begin

  582. 	write_address_pkt_channel();

  583. end

  584.           

  585.     //read operation support

  586.       else if( pkt.op == READ) 

  587.       begin    

  588. 	read_address_pkt_channel();

  589.       //put read drive logic here

  590.      end  

  591.          

  592.  	seq_item_port.item_done();

  593.  end

  594.  endtask

  595. endclass

  596.